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Julio Septién:
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- Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:396-401 [Conf]
- Sara Román, Hortensia Mecha, Daniel Mozos, Julio Septién
Partition Based Dynamic 2D HW Multitasking Management. [Citation Graph (0, 0)][DBLP] DSD, 2006, pp:61-70 [Conf]
- J. A. Maestro, Daniel Mozos, Julio Septién
A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. [Citation Graph (0, 0)][DBLP] EUROMICRO, 1998, pp:10309-10312 [Conf]
- Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:241-250 [Conf]
- Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero
2D defragmentation heuristics for hardware multitasking on reconfigurable devices. [Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf]
- Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. [Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:580-589 [Conf]
- Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz
A method for area estimation of data-path in high level synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:258-265 [Journal]
- Sara Román, Julio Septién, Hortensia Mecha, Daniel Mozos
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP] ARC, 2006, pp:187-192 [Conf]
- Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
Analyzing communication overheads during hardware/software partitioning. [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2003, v:34, n:11, pp:1001-1007 [Journal]
Resource Management for Hw Multitasking in Three Dimensional FPGAs. [Citation Graph (, )][DBLP]
FPGA Resource Management Using Internal RAM as Aata Cache. [Citation Graph (, )][DBLP]
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. [Citation Graph (, )][DBLP]
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. [Citation Graph (, )][DBLP]
3D FPGA resource management and fragmentation metric for hardware multitasking. [Citation Graph (, )][DBLP]
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