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Daniel Mozos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
    Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:396-401 [Conf]
  2. Javier Resano, Daniel Mozos
    Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:119-124 [Conf]
  3. J. A. Maestro, Daniel Mozos, Román Hermida
    The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:766-767 [Conf]
  4. J. A. Maestro, Daniel Mozos, Hortensia Mecha
    A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:218-225 [Conf]
  5. Javier Resano, Daniel Mozos, Francky Catthoor
    A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:106-111 [Conf]
  6. Sara Román, Hortensia Mecha, Daniel Mozos, Julio Septién
    Partition Based Dynamic 2D HW Multitasking Management. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:61-70 [Conf]
  7. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:156-162 [Conf]
  8. J. A. Maestro, Daniel Mozos, Julio Septién
    A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10309-10312 [Conf]
  9. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:278-279 [Conf]
  10. Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor
    Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:585-594 [Conf]
  11. Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
    A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:241-250 [Conf]
  12. Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero
    2D defragmentation heuristics for hardware multitasking on reconfigurable devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  13. E. Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
    A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  14. Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
    A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:580-589 [Conf]
  15. Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor
    A Reconfiguration Manager for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:452-460 [Journal]
  16. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:291-301 [Journal]
  17. Jesús Fernández-Conde, Daniel Mozos
    Adaptive Hybrid Broadcast for Data Dissemination in Time-Constrained Asymmetric Communication Environments. [Citation Graph (0, 0)][DBLP]
    EUROMICRO-SEAA, 2006, pp:438-447 [Conf]
  18. Sara Román, Julio Septién, Hortensia Mecha, Daniel Mozos
    Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:187-192 [Conf]
  19. Javier Resano, Daniel Mozos, Francky Catthoor
    A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  20. Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
    Analyzing communication overheads during hardware/software partitioning. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1001-1007 [Journal]

  21. HW implementation of an execution manager for reconfigurable systems. [Citation Graph (, )][DBLP]


  22. Resource Management for Hw Multitasking in Three Dimensional FPGAs. [Citation Graph (, )][DBLP]


  23. FPGA Resource Management Using Internal RAM as Aata Cache. [Citation Graph (, )][DBLP]


  24. Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. [Citation Graph (, )][DBLP]


  25. Reducing the reconfiguration overhead: a survey of techniques. [Citation Graph (, )][DBLP]


  26. FPGA support for satellite computations of hyper spectral images. [Citation Graph (, )][DBLP]


  27. Pull vs. Hybrid: Comparing Scheduling Algorithms for Asymmetric Time-Constrained Environments. [Citation Graph (, )][DBLP]


  28. Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. [Citation Graph (, )][DBLP]


  29. 3D FPGA resource management and fragmentation metric for hardware multitasking. [Citation Graph (, )][DBLP]


  30. A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. [Citation Graph (, )][DBLP]


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