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Publications of Author

1. Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima
   Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. [Citation Graph (1, 0)][DBLP]
   DAC, 1990, pp:52-57 [Conf]
   
2. Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe
   Thread partitioning method for hardware compiler bach. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:303-308 [Conf]
   
3. Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe
   Binding and Scheduling Algorithms for Highly Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:93-98 [Conf]
   
4. Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima
   Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:650-655 [Conf]
   
5. Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima
   Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. [Citation Graph (0, 0)][DBLP]
   DAC, 1990, pp:130-135 [Conf]
   
6. Nagisa Ishiura, M. Takahashi, Shuzo Yajima
   Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:497-502 [Conf]
   
7. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
   NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. [Citation Graph (0, 0)][DBLP]
   DAC, 1990, pp:8-13 [Conf]
   
8. Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
   Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:413-416 [Conf]
   
9. Hiroto Yasuura, Nagisa Ishiura
   Semantics of a Hardware Design Language for Japanese Standardization. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:836-839 [Conf]
   
10. Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima
    Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:472-475 [Conf]
    
11. Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
    Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:550-553 [Conf]
    
12. Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe
    Optimal Scheduling for Conditional Recource Sharing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2297-2300 [Conf]
    
13. Nagisa Ishiura, Masyuki Ito, Shuzo Yajima
    Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:868-875 [Journal]
    
14. Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
    High-Speed Logic Simulation on Vector Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:305-321 [Journal]
    
15. Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
    Fault simulation for multiple faults by Boolean function manipulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:531-535 [Journal]
    
16. 
    Datapath oriented codesign method of application specific DSPs using retargetable compiler. [Citation Graph (, )][DBLP]