Search the dblp DataBase

Publications of Author

1. Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya
   TITAC-2: An Asynchronous 32-bit Microprocessor. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:319-320 [Conf]
   
2. Masashi Imai, Metehan Özcan, Takashi Nanya
   Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2004, pp:62-71 [Conf]
   
3. Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
   Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2001, pp:162-172 [Conf]
   
4. Metehan Özcan, Masashi Imai, Takashi Nanya
   Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2002, pp:109-114 [Conf]
   
5. Masashi Imai, Takashi Nanya
   A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2006, pp:68-77 [Conf]
   
6. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
   Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2003, pp:184-195 [Conf]
   
7. Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
   TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:288-294 [Conf]
   
8. Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
   Asynchronous Scan-Latch controller for Low Area Overhead DFT. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:66-71 [Conf]
   
9. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
   Control signal sharing of asynchronous circuits using datapath delay information. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:617-620 [Conf]
   
10. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
    A zero-time-overhead asynchronous four-phase controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:205-208 [Conf]
    
11. Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
    High Throughput Asynchronous Domino Using Dual output Buffer. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:279-282 [Conf]
    
12. Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
    Skewed Checkpointing for Tolerating Multi-Node Failures. [Citation Graph (0, 0)][DBLP]
    SRDS, 2004, pp:116-125 [Conf]
    
13. Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:797-802 [Conf]
    
14. 
    A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. [Citation Graph (, )][DBLP]
    
    
15. 
    Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]
    
    
16. 
    Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. [Citation Graph (, )][DBLP]