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Publications of Author

1. Junhao Shi, Görschwin Fey, Rolf Drechsler
   Bridging fault testability of BDD circuits. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:188-191 [Conf]
   
2. Junhao Shi, Görschwin Fey, Rolf Drechsler
   BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:290-293 [Conf]
   
3. Görschwin Fey, Junhao Shi, Rolf Drechsler
   BDD Circuit Optimization for Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
   DSD, 2004, pp:168-172 [Conf]
   
4. Rolf Drechsler, Junhao Shi, Görschwin Fey
   MuTaTe: an efficient design for testability technique for multiplexor based circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:80-83 [Conf]
   
5. Görschwin Fey, Junhao Shi, Rolf Drechsler
   Efficiency of Multi-Valued Encoding in SAT-based ATPG. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2006, pp:25- [Conf]
   
6. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
   PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:212-217 [Conf]
   
7. Rolf Drechsler, Junhao Shi, Görschwin Fey
   Synthesis of fully testable circuits from BDDs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:440-443 [Journal]