Search the dblp DataBase
Yiorgos Makris :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Feng Shi , Yiorgos Makris SPIN-PAC: test compaction for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:71-74 [Conf ] Gennette Gill , Ankur Agiwal , Montek Singh , Feng Shi , Yiorgos Makris Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:46-56 [Conf ] Feng Shi , Yiorgos Makris A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP ] ASYNC, 2006, pp:57-67 [Conf ] Petros Drineas , Yiorgos Makris Non-Intrusive Design of Concurrently Self-Testable FSMs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2002, pp:33-0 [Conf ] Yiorgos Makris , Jamison Collins , Alex Orailoglu Fast hierarchical test path construction for DFT-free controller-datapath circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:185-190 [Conf ] Yiorgos Makris , Alex Orailoglu Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2002, pp:134-139 [Conf ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris On Concurrent Error Detection with Bounded Latency in FSMs. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:596-603 [Conf ] Sobeeh Almukhaizim , Yiorgos Makris Concurrent Error Detection in Asynchronous Burst-Mode Controllers. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:1272-1277 [Conf ] Sobeeh Almukhaizim , Yiorgos Makris Berger code-based concurrent error detection in asynchronous burst-mode machines. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:71-72 [Conf ] Petros Drineas , Yiorgos Makris Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:11164-11167 [Conf ] Yiorgos Makris , Alex Orailoglu Channel-Based Behavioral Test Synthesis for Improved Module Reachability. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:283-288 [Conf ] Sobeeh Almukhaizim , Yiorgos Makris Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:563-570 [Conf ] Yiorgos Makris , Alex Orailoglu A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. [Citation Graph (0, 0)][DBLP ] DFT, 1999, pp:339-347 [Conf ] Konstantinos Rokas , Yiorgos Makris , Dimitris Gizopoulos Low Cost Convolutional Code Based Concurrent Error Detection in FSMs. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:344-351 [Conf ] Thomas Verdel , Yiorgos Makris Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. [Citation Graph (0, 0)][DBLP ] DFT, 2002, pp:345-353 [Conf ] Feng Shi , Yiorgos Makris Fault simulation and random test generation for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2004, pp:127-130 [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Generating decision regions in analog measurement spaces. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:88-91 [Conf ] Feng Shi , Yiorgos Makris SPIN-TEST: automatic test pattern generation for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:903-908 [Conf ] Feng Shi , Yiorgos Makris Testing delay faults in asynchronous handshake circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:193-197 [Conf ] Sobeeh Almukhaizim , Thomas Verdel , Yiorgos Makris Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:194-197 [Conf ] Petros Drineas , Yiorgos Makris Independent Test Sequence Compaction through Integer Programming. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:380-386 [Conf ] Feng Shi , Sobeeh Almukhaizim , Pey-Chang Lin , Yiorgos Makris Compiler-Based Frame Formation for Static Optimization. [Citation Graph (0, 0)][DBLP ] ICCD, 2004, pp:466-471 [Conf ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris On Compaction-Based Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] IOLTS, 2003, pp:157- [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris An Analog Checker With Input-Relative Tolerance for Duplicate Signals. [Citation Graph (0, 0)][DBLP ] IOLTS, 2003, pp:54-0 [Conf ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction. [Citation Graph (0, 0)][DBLP ] ISQED, 2004, pp:459-464 [Conf ] Petros Drineas , Yiorgos Makris Concurrent Fault Detection in Random Combinational Logic. [Citation Graph (0, 0)][DBLP ] ISQED, 2003, pp:425-430 [Conf ] Yiorgos Makris , Alex Orailoglu DFT guidance through RTL test justification and propagation analysis. [Citation Graph (0, 0)][DBLP ] ITC, 1998, pp:668-0 [Conf ] Feng Shi , Yiorgos Makris SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:597-606 [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Concurrent Error Detection in Linear Analog Circuits Using State Estimation. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:1164-1173 [Conf ] Petros Drineas , Yiorgos Makris SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:167-0 [Conf ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris Cost-Driven Selection of Parity Trees. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:319-324 [Conf ] Yiorgos Makris , Ismet Bayraktaroglu , Alex Orailoglu Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:459-464 [Conf ] Yiorgos Makris , Vishal Patel , Alex Orailoglu Efficient Transparency Extraction and Utilization in Hierarchical Test. [Citation Graph (0, 0)][DBLP ] VTS, 2001, pp:246-251 [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 2003, pp:209-218 [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Constructive Derivation of Analog Specification Test Criteria. [Citation Graph (0, 0)][DBLP ] VTS, 2005, pp:395-400 [Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2006, pp:406-411 [Conf ] Andreas G. Veneris , Yiorgos Makris Session Abstract. [Citation Graph (0, 0)][DBLP ] VTS, 2006, pp:290-291 [Conf ] Haralampos-G. D. Stratigopoulos , Petros Drineas , Mustapha Slamani , Yiorgos Makris Non-RF to RF Test Correlation Using Learning Machines: A Case Study. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:9-14 [Conf ] Sobeeh Almukhaizim , Yiorgos Makris Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2007, v:56, n:6, pp:785-798 [Journal ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1547-1554 [Journal ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Nonlinear decision boundaries for testing analog circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1760-1773 [Journal ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Concurrent detection of erroneous responses in linear analog circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:878-891 [Journal ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris Compaction-based concurrent error detection for digital circuits. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2005, v:36, n:9, pp:856-862 [Journal ] Yiorgos Makris , Alex Orailoglu On the identification of modular test requirements for low cost hierarchical test path construction. [Citation Graph (0, 0)][DBLP ] Integration, 2007, v:40, n:3, pp:315-325 [Journal ] Yiorgos Makris , Ismet Bayraktaroglu , Alex Orailoglu Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. [Citation Graph (0, 0)][DBLP ] IEEE Transactions on Reliability, 2004, v:53, n:2, pp:269-278 [Journal ] Enrichment of limited training sets in machine-learning-based analog/RF test. [Citation Graph (, )][DBLP ] Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. [Citation Graph (, )][DBLP ] Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors. [Citation Graph (, )][DBLP ] On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. [Citation Graph (, )][DBLP ] A Statistical Approach to Characterizing and Testing Functionalized Nanowires. [Citation Graph (, )][DBLP ] Hardware Trojan Detection Using Path Delay Fingerprint. [Citation Graph (, )][DBLP ] Experiences in Hardware Trojan Design and Implementation. [Citation Graph (, )][DBLP ] Hardware Trojans in Wireless Cryptographic ICs. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.303secs