Keoncheol Shin, Taewhan Kim Leakage power minimization for the synthesis of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:166-169 [Conf]
Keoncheol Shin, Taewhan Kim Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:766-775 [Journal]