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Jihong Kim :
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Dongkun Shin , Jihong Kim Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:653-658 [Conf ] Dongkun Shin , Jihong Kim Optimizing intra-task voltage scheduling using data flow analysis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:703-708 [Conf ] Han-Saem Yun , Jihong Kim , Soo-Mook Moon A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows. [Citation Graph (0, 0)][DBLP ] CC, 2001, pp:182-199 [Conf ] Sungtaek Lim , Jihong Kim , Kiyoung Choi Scheduling-based code size reduction in processors with indirect addressing mode. [Citation Graph (0, 0)][DBLP ] CODES, 2001, pp:165-169 [Conf ] Dongkun Shin , Jihong Kim Power-aware communication optimization for networks-on-chips with voltage scalable links. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:170-175 [Conf ] Dongkun Shin , Jihong Kim , Seongsoo Lee Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:438-443 [Conf ] Woonseok Kim , Jihong Kim , Sang Lyul Min A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:788-794 [Conf ] Dongkun Shin , Jihong Kim , Naehyuck Chang An operation rearrangement technique for power optimization in VLIM instruction fetch. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:809- [Conf ] Young-Jin Kim , Kwon-Taek Kwon , Jihong Kim Energy-efficient file placement techniques for heterogeneous mobile storage systems. [Citation Graph (0, 0)][DBLP ] EMSOFT, 2006, pp:171-177 [Conf ] Dongkun Shin , Jihong Kim Power-Aware Scheduling of Mixed Task Sets in Priority-Driven Systems. [Citation Graph (0, 0)][DBLP ] EUC, 2004, pp:227-237 [Conf ] Keun Soo Yim , Jihong Kim , Kern Koh An Energy-Efficient Routing and Reporting Scheme to Exploit Data Similarities in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] EUC, 2004, pp:515-527 [Conf ] Chun-Mok Chung , Jihong Kim , Dohyung Kim Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:126-131 [Conf ] Keun Soo Yim , Jihong Kim , Kern Koh An Energy-Efficient Reliable Transport for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] ICOIN, 2004, pp:54-64 [Conf ] Han-Saem Yun , Jihong Kim , Soo-Mook Moon Optimal software pipelining of loops with control flows. [Citation Graph (0, 0)][DBLP ] ICS, 2002, pp:117-128 [Conf ] Woongki Baek , Jihong Kim Load-store reordering for low-power multimedia data transfers. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2005, pp:2715-2718 [Conf ] Woonseok Kim , Jihong Kim , Sang Lyul Min Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:396-401 [Conf ] Woonseok Kim , Jihong Kim , Sang Lyul Min Preemption-aware dynamic voltage scaling in hard real-time systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 2004, pp:393-398 [Conf ] Dongkun Shin , Jihong Kim A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:271-274 [Conf ] Dongkun Shin , Jihong Kim Power-aware scheduling of conditional task graphs in real-time multiprocessor systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:408-413 [Conf ] Han-Saem Yun , Jihong Kim Power-aware modulo scheduling for high-performance VLIW processors. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:40-45 [Conf ] Keun Soo Yim , Jang-Soo Lee , Jihong Kim , Shin-Dug Kim , Kern Koh A Space-Efficient On-Chip Compressed Cache Organization for High Performance Computing. [Citation Graph (0, 0)][DBLP ] ISPA, 2004, pp:952-964 [Conf ] Dongkun Shin , Woonseok Kim , Jaekwon Jeon , Jihong Kim , Sang Lyul Min SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms. [Citation Graph (0, 0)][DBLP ] PACS, 2002, pp:141-156 [Conf ] Keun Soo Yim , Jihong Kim , Kern Koh Performance Analysis of On-Chip Cache and Main Memory Compression Systems for High-End Parallel Computers. [Citation Graph (0, 0)][DBLP ] PDPTA, 2004, pp:469-475 [Conf ] Woonseok Kim , Dongkun Shin , Han-Saem Yun , Jihong Kim , Sang Lyul Min Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP ] IEEE Real Time Technology and Applications Symposium, 2002, pp:219-228 [Conf ] Young-Jin Kim , Jihong Kim Exploration of Memory-Aware Dynamic Voltage Scheduling for Soft Real-Time Applications. [Citation Graph (0, 0)][DBLP ] RTCSA, 2005, pp:177-180 [Conf ] Sung-Soo Lim , Jihong Kim , Sang Lyul Min A Worst Case Timing Analysis Technique for Optimized Programs. [Citation Graph (0, 0)][DBLP ] RTCSA, 1998, pp:151-157 [Conf ] Keun Soo Yim , Jeong-Joon Yoo , Jae Don Lee , Jihong Kim Operating System Support for Procedural Abstraction in Embedded Systems. [Citation Graph (0, 0)][DBLP ] RTCSA, 2006, pp:378-384 [Conf ] Sung-Soo Lim , Jung Hee Han , Jihong Kim , Sang Lyul Min A Worst Case Timing Analysis Technique for Multiple-Issue Machines. [Citation Graph (0, 0)][DBLP ] IEEE Real-Time Systems Symposium, 1998, pp:334-345 [Conf ] Keun Soo Yim , Jihong Kim , Kern Koh A fast start-up technique for flash memory based computing systems. [Citation Graph (0, 0)][DBLP ] SAC, 2005, pp:843-849 [Conf ] Young-Jin Kim , Kwon-Taek Kwon , Jihong Kim Energy-efficient disk replacement and file placement techniques for mobile systems with hard disks. [Citation Graph (0, 0)][DBLP ] SAC, 2007, pp:693-698 [Conf ] Jihong Kim , Yongmin Kim Efficient 2-D Convolution Algorithm with the Single-Data Multiple Kernel Approach. [Citation Graph (0, 0)][DBLP ] CVGIP: Graphical Model and Image Processing, 1995, v:57, n:2, pp:175-182 [Journal ] Jihong Kim , Yongmin Kim Simulating Multimedia Systems with MVPSIM. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1995, v:12, n:4, pp:18-27 [Journal ] Dongkun Shin , Jihong Kim , Seongsoo Lee Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2001, v:18, n:2, pp:20-30 [Journal ] Dongkun Shin , Hojun Shim , Yongsoo Joo , Han-Saem Yun , Jihong Kim , Naehyuck Chang Energy-Monitoring Tool for Low-Power Embedded Programs. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2002, v:19, n:4, pp:7-17 [Journal ] Han-Saem Yun , Jihong Kim , Soo-Mook Moon Time Optimal Software Pipelining of Loops with Control Flows. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2003, v:31, n:5, pp:339-391 [Journal ] Yonghyun Hwang , Jihong Kim , Eunkyong Seo Structure-Aware Web Transcoding for Mobile Devices. [Citation Graph (0, 0)][DBLP ] IEEE Internet Computing, 2003, v:7, n:5, pp:14-21 [Journal ] Jihong Kim , Yongmin Kim UWICL: A Multi-Layered Parallel Image Computing Library for Single-Chip Multiprocessor-based Time-Critical Systems. [Citation Graph (0, 0)][DBLP ] Real-Time Imaging, 1996, v:2, n:3, pp:187-199 [Journal ] Dongkun Shin , Jihong Kim Intra-task voltage scheduling on DVS-enabled hard real-time systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1530-1549 [Journal ] Dongkun Shin , Jihong Kim Dynamic voltage scaling of mixed task sets in priority-driven systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:438-453 [Journal ] Han-Saem Yun , Jihong Kim On energy-optimal voltage scheduling for fixed-priority hard real-time systems. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:393-430 [Journal ] Young-Jin Kim , Jihong Kim Device-Aware Cache Replacement Algorithm for Heterogeneous Mobile Storage Devices. [Citation Graph (0, 0)][DBLP ] ICESS, 2007, pp:13-24 [Conf ] Woonseok Kim , Dongkun Shin , Han-Saem Yun , Jihong Kim , Sang Lyul Min Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2005, v:1, n:3, pp:207-216 [Journal ] Dongkun Shin , Jihong Kim Communication Power Optimization for Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2006, v:2, n:2, pp:165-176 [Journal ] A Low-Power Implementation of 3D Graphics System for Embedded Mobile Systems. [Citation Graph (, )][DBLP ] A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. [Citation Graph (, )][DBLP ] Replication-aware leakage management in chip multiprocessors with private L2 cache. [Citation Graph (, )][DBLP ] Search in 0.009secs, Finished in 0.012secs