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Hideyuki Ichihara:
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- Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue
A Huffman-based coding with efficient test application. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:75-78 [Conf]
- Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
An Effective Design for Hierarchical Test Generation Based on Strong Testability. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:288-293 [Conf]
- Hideyuki Ichihara, Kozo Kinoshita
On Acceleration of Logic Circuits Optimization Using Implication Relations. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1997, pp:222-227 [Conf]
- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1998, pp:58-63 [Conf]
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1999, pp:147-152 [Conf]
- Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura
Dynamic Test Compression Using Statistical Coding. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2001, pp:143-0 [Conf]
- Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
A Test Decompression Scheme for Variable-Length Coding. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2004, pp:426-431 [Conf]
- Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue
Test Response Compression Based on Huffman Coding. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2003, pp:446-451 [Conf]
- Hideyuki Ichihara, Tomoo Inoue
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:11180-11181 [Conf]
- Hideyuki Ichihara, Tomoo Inoue
Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding. [Citation Graph (0, 0)][DBLP] DELTA, 2002, pp:396-402 [Conf]
- Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue
A Reconfigurable Embedded Decompressor for Test Compression. [Citation Graph (0, 0)][DBLP] DELTA, 2006, pp:301-308 [Conf]
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On Test Generation with A Limited Number of Tests. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:12-15 [Conf]
- Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:329-334 [Conf]
- Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
Test Transformation to Improve Compaction by Statistical Encoding. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:294-299 [Conf]
- Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
TAM Design and Optimization for Transparency-Based SoC Test. [Citation Graph (0, 0)][DBLP] VTS, 2007, pp:381-388 [Conf]
- Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue
Huffman-Based Test Response Coding. [Citation Graph (0, 0)][DBLP] IEICE Transactions, 2005, v:88, n:1, pp:158-161 [Journal]
- Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
Test cost reduction for logic circuits: Reduction of test data volume and test application time. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2005, v:36, n:6, pp:69-83 [Journal]
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On invariant implication relations for removing partial circuits. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 1997, v:28, n:7, pp:39-47 [Journal]
- Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2007, pp:117-124 [Conf]
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. [Citation Graph (, )][DBLP]
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic. [Citation Graph (, )][DBLP]
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System. [Citation Graph (, )][DBLP]
Hybrid test application in hybrid delay scan design. [Citation Graph (, )][DBLP]
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