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Publications of Author

1. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
   Leakage control in FPGA routing fabric. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:661-664 [Conf]
   
2. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
   FLAW: FPGA lifetime awareness. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:630-635 [Conf]
   
3. Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
   Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:218-223 [Conf]
   
4. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
   Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:107-110 [Conf]
   
5. I.-C. Lin, S. Srinivasan, Narayanan Vijaykrishnan, N. Dhanwada
   Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:775-780 [Conf]
   
6. Suresh Srinivasan, Narayanan Vijaykrishnan
   Variation Aware Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:422-423 [Conf]
   
7. 
   FPGA routing architecture analysis under variations. [Citation Graph (, )][DBLP]
   
   
8. 
   A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. [Citation Graph (, )][DBLP]
   
   
9. 
   Leakage Optimized DECAP Design for FPGAs. [Citation Graph (, )][DBLP]
   
   
10. 
    Combining Lexical and Semantic Methods of Inter-terminology Mapping Using the UMLS. [Citation Graph (, )][DBLP]