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Aman Gayasen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
    Leakage control in FPGA routing fabric. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:661-664 [Conf]
  2. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin
    Exploring technology alternatives for nano-scale FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:921-926 [Conf]
  3. Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman
    Switch Box Architectures for Three-Dimensional FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:335-336 [Conf]
  4. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    Reducing leakage energy in FPGAs using region-constrained placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:51-58 [Conf]
  5. Aman Gayasen
    Low Power Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1169- [Conf]
  6. Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    A Dual-VDD Low Power FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:145-157 [Conf]
  7. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
    Improving soft-error tolerance of FPGA configuration bits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:107-110 [Conf]
  8. Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
    Thermal characterization and optimization in platform FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:443-447 [Conf]
  9. Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo
    Improving Java Performance Using Dynamic Method Migration on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  10. Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
    Assessing carbon nanotube bundle interconnect for future FPGA architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:307-312 [Conf]

  11. A Hardware Efficient Support Vector Machine Architecture for FPGA. [Citation Graph (, )][DBLP]


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