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Xiaoping Tang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Optimal redistribution of white space for wire length minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:412-417 [Conf]
  2. Xiaoping Tang, D. F. Wong
    FAST-SP: a fast algorithm for block placement based on sequence pair. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:521-526 [Conf]
  3. Xiaoping Tang, Martin D. F. Wong
    On handling arbitrary rectilinear shape constraint. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:38-41 [Conf]
  4. Xiaoping Tang, Martin D. F. Wong
    Tradeoff routing resource, runtime and quality in buffered routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:430-433 [Conf]
  5. Xiaoping Tang, D. F. Wong
    Floorplanning with alignment and performance constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:848-853 [Conf]
  6. Hua Xiang, D. F. Wong, Xiaoping Tang
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:584-589 [Conf]
  7. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
    A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:470-477 [Conf]
  8. Xiaoping Tang, D. F. Wong, Ruiqi Tian
    Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:106-111 [Conf]
  9. Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
    A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:49-56 [Conf]
  10. Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong
    On mask layout partitioning for electron projection lithography. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:514-518 [Conf]
  11. Hua Xiang, Xiaoping Tang, D. F. Wong
    An Algorithm for Simultaneous Pin Assignment and Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:232-0 [Conf]
  12. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:66-73 [Conf]
  13. Xiaoping Tang, Xin Yuan
    Technology migration techniques for simplified layouts with restrictive design rules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:655-660 [Conf]
  14. Xiaoping Tang, D. F. Wong
    Planning buffer locations by network flows. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:180-185 [Conf]
  15. Ruiqi Tian, Xiaoping Tang, D. F. Wong
    Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:118-123 [Conf]
  16. Xiaoping Tang, D. F. Wong
    Network flow based buffer planning. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:30, n:2, pp:143-155 [Journal]
  17. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
  18. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1406-1413 [Journal]
  19. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
    Minimizing wire length in floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1744-1753 [Journal]
  20. Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong
    Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:63-71 [Journal]
  21. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Min-cost flow-based algorithm for simultaneous pin assignment and routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:870-878 [Journal]
  22. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1522-1530 [Journal]
  23. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:561-572 [Journal]

  24. Practical method for obtaining a feasible integer solution in hierarchical layout optimization. [Citation Graph (, )][DBLP]


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