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P. R. Suresh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh
    Transistor Flaring in Deep Submicron-Design Considerations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:299-304 [Conf]
  2. N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das
    Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:518-523 [Conf]
  3. Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh
    A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:192-0 [Conf]
  4. Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh
    Transistor Flaring in Deep Submicron-Design Considerations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:299-304 [Conf]
  5. P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala
    Package-silicon co-design - Experiment with an SOC design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:531-0 [Conf]

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