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Publications of Author

1. Debjit Sinha, Hai Zhou
   Yield driven gate sizing for coupling-noise reduction under uncertainty. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:192-197 [Conf]
   
2. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
   Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:618-623 [Conf]
   
3. Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
   An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:256- [Conf]
   
4. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
   Statistical gate sizing for timing yield optimization. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:1037-1041 [Conf]
   
5. Debjit Sinha, Hai Zhou
   Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:14-19 [Conf]
   
6. Debjit Sinha, Hai Zhou
   A unified framework for statistical timing analysis with coupling and multiple input switching. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:837-843 [Conf]
   
7. Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
   A timing dependent power estimation framework considering coupling. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:401-407 [Conf]
   
8. Debjit Sinha, Hai Zhou, Chris C. N. Chu
   Optimal gate sizing for coupling-noise reduction. [Citation Graph (0, 0)][DBLP]
   ISPD, 2004, pp:176-181 [Conf]
   
9. Debjit Sinha, Hai Zhou, Narendra V. Shenoy
   Advances in Computation of the Maximum of a Set of Random Variables. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:306-311 [Conf]
   
10. Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
    Yield-Aware Cache Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:15-25 [Conf]
    
11. Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
    Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:875-880 [Conf]
    
12. Debjit Sinha, Hai Zhou
    Gate-size optimization under timing constraints for coupling-noise reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1064-1074 [Journal]
    
13. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
    Statistical Timing Yield Optimization by Gate Sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1140-1146 [Journal]
    
14. 
    Driver waveform computation for timing analysis with multiple voltage threshold driver models. [Citation Graph (, )][DBLP]
    
    
15. 
    Constrained aggressor set selection for maximum coupling noise. [Citation Graph (, )][DBLP]