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## Search the dblp DataBase
Hai Zhou:
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## Publications of Author- Debjit Sinha, Hai Zhou
**Yield driven gate sizing for coupling-noise reduction under uncertainty.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:192-197 [Conf] - Jia Wang, Hai Zhou
**Interconnect estimation without packing via ACG floorplans.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1152-1155 [Conf] - Hai Zhou
**Deriving a new efficient algorithm for min-period retiming.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:990-993 [Conf] - Hai Zhou, Narendra V. Shenoy, William Nicholls
**Efficient minimum spanning tree construction without Delaunay triangulation.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:192-197 [Conf] - Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
**Efficient octilinear Steiner tree construction based on spanning graphs.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:687-690 [Conf] - Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
**An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:28-33 [Conf] - Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
**BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.**[Citation Graph (0, 0)][DBLP] CAV, 1998, pp:244-255 [Conf] - Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
**Incremental exploration of the combined physical and behavioral design space.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:208-213 [Conf] - Chuan Lin, Hai Zhou
**An efficient retiming algorithm under setup and hold constraints.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:945-950 [Conf] - Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
**Leakage power optimization with dual-V**[Citation Graph (0, 0)][DBLP]_{th}library in high-level synthesis. DAC, 2005, pp:202-207 [Conf] - Jia Wang, Hai Zhou
**Optimal jumper insertion for antenna avoidance under ratio upper-bound.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:761-766 [Conf] - Hai Zhou, Narendra V. Shenoy, William Nicholls
**Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:714-719 [Conf] - Hai Zhou, D. F. Wong
**Optimal low power X OR gate decomposition.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:104-107 [Conf] - Hai Zhou, D. F. Wong
**Global Routing with Crosstalk Constraints.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:374-377 [Conf] - Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
**Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:96-99 [Conf] - Chuan Lin, Hai Zhou
**Wire Retiming for System-on-Chip by Fixpoint Computation.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1092-1097 [Conf] - Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
**Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:618-623 [Conf] - Hai Zhou
**Timing Verification with Crosstalk for Transparently Latched Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10056-10061 [Conf] - Jia Wang, Hai Zhou
**Minimal period retiming under process variations.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:131-135 [Conf] - Jia Wang, Ming-Yang Kao, Hai Zhou
**Address generation for nanowire decoders.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:525-528 [Conf] - Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
**NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:25-30 [Conf] - Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
**Track assignment: a desirable intermediate step between global routing and detailed routing.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:59-66 [Conf] - Ruiming Chen, Hai Zhou
**Timing macro-modeling of IP blocks with crosstalk.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:155-159 [Conf] - Ruiming Chen, Hai Zhou
**Clock schedule verification under process variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:619-625 [Conf] - Ruiming Chen, Hai Zhou
**Efficient algorithms for buffer insertion in general circuits based on network flow.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:322-326 [Conf] - Chung-Ping Chen, Hai Zhou, D. F. Wong
**Optimal non-uniform wire-sizing under the Elmore delay model.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:38-43 [Conf] - Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
**Integrated floorplanning and interconnect planning.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:354-357 [Conf] - Chuan Lin, Jia Wang, Hai Zhou
**Clustering for processing rate optimization.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:189-195 [Conf] - Chuan Lin, Hai Zhou
**Retiming for Wire Pipelining in System-On-Chip.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:215-220 [Conf] - Chuan Lin, Hai Zhou
**Optimal wire retiming without binary search.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:452-458 [Conf] - Chuan Lin, Hai Zhou
**Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:329-334 [Conf] - Debjit Sinha, Narendra V. Shenoy, Hai Zhou
**Statistical gate sizing for timing yield optimization.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:1037-1041 [Conf] - Debjit Sinha, Hai Zhou
**Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:14-19 [Conf] - Debjit Sinha, Hai Zhou
**A unified framework for statistical timing analysis with coupling and multiple input switching.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:837-843 [Conf] - Hai Zhou, D. F. Wong
**An optimal algorithm for river routing with crosstalk constraints.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:310-315 [Conf] - Hai Zhou, D. F. Wong
**An exact gate decomposition algorithm for low-power technology mapping.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:575-580 [Conf] - Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
**A timing dependent power estimation framework considering coupling.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:401-407 [Conf] - Chuan Lin, Hai Zhou, Chris Chu
**A revisit to floorplan optimization by Lagrangian relaxation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:164-171 [Conf] - Ruiming Chen, Hai Zhou
**A Flexible Data Structure for Efficient Buffer Insertion.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:216-221 [Conf] - I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
**An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:210-215 [Conf] - Hai Zhou, Jia Wang
**ACG-Adjacent Constraint Graph for General Floorplans.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:572-575 [Conf] - Hai Zhou, D. F. Wong
**Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:628-633 [Conf] - Min Pan, Chris C. N. Chu, Hai Zhou
**Timing yield estimation using statistical static timing analysis.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2461-2464 [Conf] - Debjit Sinha, Hai Zhou, Chris C. N. Chu
**Optimal gate sizing for coupling-noise reduction.**[Citation Graph (0, 0)][DBLP] ISPD, 2004, pp:176-181 [Conf] - Hai Zhou
**Efficient Steiner tree construction based on spanning graphs.**[Citation Graph (0, 0)][DBLP] ISPD, 2003, pp:152-157 [Conf] - Hai Zhou, Adnan Aziz
**Buffer minimization in pass transistor logic.**[Citation Graph (0, 0)][DBLP] ISPD, 2000, pp:105-110 [Conf] - Debjit Sinha, Hai Zhou, Narendra V. Shenoy
**Advances in Computation of the Maximum of a Set of Random Variables.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:306-311 [Conf] - Jia Wang, Hai Zhou, Ping-Chih Wu
**Processing Rate Optimization by Sequential System Floorplanning.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:340-345 [Conf] - Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
**Yield-Aware Cache Architectures.**[Citation Graph (0, 0)][DBLP] MICRO, 2006, pp:15-25 [Conf] - Hai Zhou
**Clock schedule verification with crosstalk.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:78-83 [Conf] - Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
**Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:875-880 [Conf] - Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
**BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.**[Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 2003, v:22, n:3, pp:205-224 [Journal] - Hai Zhou, Narendra V. Shenoy, William Nicholls
**Efficient minimum spanning tree construction without Delaunay triangulation.**[Citation Graph (0, 0)][DBLP] Inf. Process. Lett., 2002, v:81, n:5, pp:271-276 [Journal] - Ruiming Chen, Hai Zhou
**Statistical timing verification for transparently latched circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1847-1855 [Journal] - Chuan Lin, Hai Zhou
**Optimal wire retiming without binary search.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1577-1588 [Journal] - Debjit Sinha, Hai Zhou
**Gate-size optimization under timing constraints for coupling-noise reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1064-1074 [Journal] - Hai Zhou
**Timing analysis with crosstalk is a fixpoint on a complete lattice.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1261-1269 [Journal] - Hai Zhou
**Efficient Steiner tree construction based on spanning graphs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:704-710 [Journal] - Hai Zhou, Adnan Aziz
**Buffer minimization in pass transistor logic.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:693-697 [Journal] - Hai Zhou, Chuan Lin
**Retiming for wire pipelining in system-on-chip.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1338-1345 [Journal] - Hai Zhou, Martin D. F. Wong
**Global routing with crosstalk constraints.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1683-1688 [Journal] - Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
**Simultaneous routing and buffer insertion with restrictions onbuffer locations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:819-824 [Journal] - Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
**Spanning graph-based nonrectilinear steiner tree algorithms.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1066-1075 [Journal] - Hai Zhou, D. F. Wong
**Optimal river routing with crosstalk constraints.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:496-514 [Journal] - Chuan Lin, Hai Zhou
**Wire retiming as fixpoint computation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1340-1348 [Journal] - Debjit Sinha, Narendra V. Shenoy, Hai Zhou
**Statistical Timing Yield Optimization by Gate Sizing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1140-1146 [Journal] - Ruiming Chen, Hai Zhou
**Fast Min-Cost Buffer Insertion under Process Variations.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:338-343 [Conf] - Chuan Lin, Aiguo Xie, Hai Zhou
**Design closure driven delay relaxation based on convex cost network flow.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:63-68 [Conf] - Chuan Lin, Jia Wang, Hai Zhou
**Clustering for Processing Rate Optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1264-1275 [Journal] **Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.**[Citation Graph (, )][DBLP]**Fast Buffer Insertion for Yield Optimization Under Process Variations.**[Citation Graph (, )][DBLP]**Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.**[Citation Graph (, )][DBLP]**Retiming for Synchronous Data Flow Graphs.**[Citation Graph (, )][DBLP]**New Block-Based Statistical Timing Analysis Approaches Without Moment Matching.**[Citation Graph (, )][DBLP]**A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications.**[Citation Graph (, )][DBLP]**Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.**[Citation Graph (, )][DBLP]**Risk aversion min-period retiming under process variations.**[Citation Graph (, )][DBLP]**Exploring adjacency in floorplanning.**[Citation Graph (, )][DBLP]**An efficient incremental algorithm for min-area retiming.**[Citation Graph (, )][DBLP]**Multicore parallel min-cost flow algorithm for CAD applications.**[Citation Graph (, )][DBLP]**Provably good and practically efficient algorithms for CMP dummy fill.**[Citation Graph (, )][DBLP]**Statistical reliability analysis under process variation and aging effects.**[Citation Graph (, )][DBLP]**Exception triggered DoS attacks on wireless networks.**[Citation Graph (, )][DBLP]**State space abstraction for parameterized self-stabilizing embedded systems.**[Citation Graph (, )][DBLP]**Retiming and resynthesis with sweep are complete for sequential transformation.**[Citation Graph (, )][DBLP]**3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.**[Citation Graph (, )][DBLP]**Timing budgeting under arbitrary process variations.**[Citation Graph (, )][DBLP]**Gate sizing by Lagrangian relaxation revisited.**[Citation Graph (, )][DBLP]**Binning optimization based on SSTA for transparently-latched circuits.**[Citation Graph (, )][DBLP]**Linear constraint graph for floorplan optimization with soft blocks.**[Citation Graph (, )][DBLP]**FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.**[Citation Graph (, )][DBLP]**Hybrid energy storage system integration for vehicles.**[Citation Graph (, )][DBLP]**An**[Citation Graph (, )][DBLP]*O*(*n*log*n*) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.**An efficient current-based logic cell model for crosstalk delay analysis.**[Citation Graph (, )][DBLP]
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