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Andreas G. Veneris: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexander Smith, Andreas G. Veneris, Anastasios Viglas
    Design diagnosis using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:218-223 [Conf]
  2. Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
    Design rewiring based on diagnosis techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:479-484 [Conf]
  3. Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
    Efficient SAT-based Boolean matching for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:466-471 [Conf]
  4. Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    On the relation between simulation-based and SAT-based diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1139-1144 [Conf]
  5. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
    Managing Don't Cares in Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:260-265 [Conf]
  6. Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
    Incremental Diagnosis and Correction of Multiple Faults and Errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:716-721 [Conf]
  7. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:996-1001 [Conf]
  8. Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
    Diagnosing multiple transition faults in the absence of timing information. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:193-196 [Conf]
  9. Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
    Utilizing don't care states in SAT-based bounded sequential problems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:264-269 [Conf]
  10. Andreas G. Veneris, Ibrahim N. Hajj
    A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:45-50 [Conf]
  11. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:871-876 [Conf]
  12. Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
    Debugging sequential circuits using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:204-209 [Conf]
  13. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri
    Fault equivalence and diagnostic test generation using ATPG. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:221-224 [Conf]
  14. Andreas G. Veneris, Ibrahim N. Hajj
    Correcting multiple design errors in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:31-34 [Conf]
  15. Mandana Amiri, Andreas G. Veneris, Ivor Ting
    Design rewiring for power minimization [logic design]. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:305-308 [Conf]
  16. Elham Safi, Andreas Moshovos, Andreas G. Veneris
    L-CBF: a low-power, fast counting bloom filter architecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:250-255 [Conf]
  17. Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi
    Incremental Diagnosis of Multiple Open-Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1085-1092 [Conf]
  18. Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
    Design Rewiring Using ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:223-232 [Conf]
  19. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Diagnosis and Correction in High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:423-430 [Conf]
  20. Sean Safarpour, Andreas G. Veneris
    Abstraction and Refinement Techniques in Automated Design Debugging. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:88-93 [Conf]
  21. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-Verification Debugging of Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:42-47 [Conf]
  22. Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith
    Debugging Sequential Circuits Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:44-49 [Conf]
  23. Andreas G. Veneris
    Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:60-0 [Conf]
  24. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:54-59 [Conf]
  25. Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs
    Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:58-63 [Conf]
  26. Andreas G. Veneris, Yiorgos Makris
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:290-291 [Conf]
  27. Lefteris M. Kirousis, Andreas G. Veneris
    Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. [Citation Graph (0, 0)][DBLP]
    WDAG, 1993, pp:54-68 [Conf]
  28. Lefteris M. Kirousis, Andreas G. Veneris
    Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1995, v:32, n:2, pp:155-170 [Journal]
  29. Andreas G. Veneris
    Logic Rewiring for Delay and Power Minimization. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2004, v:20, n:6, pp:1231-1238 [Journal]
  30. Jiang Brandon Liu, Andreas G. Veneris
    Incremental fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:240-251 [Journal]
  31. Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas
    Fault diagnosis and logic debugging using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1606-1621 [Journal]
  32. Andreas G. Veneris, Magdy S. Abadir
    Design rewiring using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1469-1479 [Journal]
  33. Andreas G. Veneris, Ibrahim N. Hajj
    Design error diagnosis and correction via test vector simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1803-1816 [Journal]
  34. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction error modeling and automated model debugging in high-performance custom designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:763-776 [Journal]
  35. Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
    Maximum circuit activity estimation using pseudo-boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1538-1543 [Conf]
  36. Sean Safarpour, Andreas G. Veneris
    Abstraction and refinement techniques in automated design debugging. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1182-1187 [Conf]
  37. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    Integrating observability don't cares in all-solution SAT solvers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi
    Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:495-502 [Journal]
  39. Andreas G. Veneris, Jiang Brandon Liu
    Incremental Design Debugging in a Logic Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:485-494 [Journal]

  40. Automating Logic Rectification by Approximate SPFDs. [Citation Graph (, )][DBLP]


  41. Trace Compaction using SAT-based Reachability Analysis. [Citation Graph (, )][DBLP]


  42. The day Sherlock Holmes decided to do EDA. [Citation Graph (, )][DBLP]


  43. Automated data analysis solutions to silicon debug. [Citation Graph (, )][DBLP]


  44. Sequential logic rectifications with approximate SPFDs. [Citation Graph (, )][DBLP]


  45. Leveraging dominators for preprocessing QBF. [Citation Graph (, )][DBLP]


  46. Scaling VLSI design debugging with interpolation. [Citation Graph (, )][DBLP]


  47. Improved Design Debugging Using Maximum Satisfiability. [Citation Graph (, )][DBLP]


  48. Spatial and temporal design debug using partial MaxSAT. [Citation Graph (, )][DBLP]


  49. A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. [Citation Graph (, )][DBLP]


  50. A succinct memory model for automated design debugging. [Citation Graph (, )][DBLP]


  51. On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. [Citation Graph (, )][DBLP]


  52. A physical level study and optimization of CAM-based checkpointed register alias table. [Citation Graph (, )][DBLP]


  53. On the latency, energy and area of checkpointed, superscalar register alias tables. [Citation Graph (, )][DBLP]


  54. Automated silicon debug data analysis techniques for a hardware data acquisition environment. [Citation Graph (, )][DBLP]


  55. A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. [Citation Graph (, )][DBLP]


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