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Publications of Author

1. Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
   Power minimization for dynamic PLAs. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1010-1013 [Conf]
   
2. De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
   Timing driven power gating. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:121-124 [Conf]
   
3. Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
   A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. [Citation Graph (0, 0)][DBLP]
   DATE Designers' Forum, 2006, pp:239-243 [Conf]
   
4. Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
   An 830mW, 586kbps 1024-bit RSA chip design. [Citation Graph (0, 0)][DBLP]
   DATE Designers' Forum, 2006, pp:24-29 [Conf]
   
5. Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
   A low-power high-SFDR CMOS direct digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1670-1673 [Conf]
   
6. Chingwei Yeh, Yin-Shuin Kang
   A simulated annealing based method supporting dual supply voltages in standard cell placement. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:310-313 [Conf]
   
7. Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
   Power reduction through iterative gate sizing and voltage scaling. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:246-249 [Conf]
   
8. Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
   A cell selection strategy for low power applications. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 1999, pp:416-419 [Conf]
   
9. Chingwei Yeh, Chi-Shong Wang
   On the integration of partitioning and global routing for rectilinear placement problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:83-91 [Journal]
   
10. Chi-Shong Wang, Chingwei Yeh
    Performance-driven technology mapping with MSG partition and selective gate duplication. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:953-973 [Journal]
    
11. Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
    Power minimization for dynamic PLAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:616-624 [Journal]
    
12. Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
    Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:105-119 [Conf]
    
13. Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
    Design of STR level converters for SoCs using the multi-island dual-VDD design technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
14. Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel
    Block-oriented programmable design with switching network interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:45-53 [Journal]
    
15. Chingwei Yeh, Yin-Shuin Kang
    Cell-based layout techniques supporting gate-level voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:629-633 [Journal]
    
16. Chingwei Yeh, Yin-Shuin Kang
    Cell-based layout techniques supporting gate-level voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:983-986 [Journal]