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Seyed Mojtaba Atarodi:
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Publications of Author
- Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
A fractional delay-locked loop for on chip clock generation applications. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1300-1309 [Conf]
- Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:258-263 [Conf]
- Hesam Amir Aslanzadeh, Saeid Mehrmanesh, M. B. Vahidfar, Seyed Mojtaba Atarodi
A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:885-888 [Conf]
- Saeid Mehrmanesh, Seyed Mojtaba Atarodi, Hesam Amir Aslanzadeh, Saeed Saeedi, Amin Quasem Safarian
A new full CMOS 2.5 V two-stage line driver with variable gain for ADSL applications. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:405-408 [Conf]
- Saeid Mehrmanesh, Hesam Amir Aslanzadeh, M. B. Vahidfar, Seyed Mojtaba Atarodi
A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:273-276 [Conf]
- Saeid Mehrmanesh, M. B. Vahidfar, Hesam Amir Aslanzadeh, Seyed Mojtaba Atarodi
A 1-volt, high PSRR, CMOS bandgap voltage reference. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:381-384 [Conf]
- Saeid Mehrmanesh, M. B. Vahidfar, Hesam Amir Aslanzadeh, Seyed Mojtaba Atarodi
An ultra low-voltage Gm-C filter for video applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:561-564 [Conf]
- Saeed Saeedi, Saeid Mehrmanesh, Seyed Mojtaba Atarodi, Hesam Amir Aslanzadeh
A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:349-352 [Conf]
- Amin Quasem Safarian, F. Sahandi, Seyed Mojtaba Atarodi
A new low-power sigma-delta modulator with the reduced number of op-amps for speech band applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:1033-1036 [Conf]
- Armin Tajalli, Seyed Mojtaba Atarodi
A compact biquadratic g/sub m/-C filter structure for low-voltage and high frequency applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:501-504 [Conf]
- Armin Tajalli, Seyed Mojtaba Atarodi
Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:521-524 [Conf]
- Armin Tajalli, Seyed Mojtaba Atarodi
Structured design of an integrated subscriber line interface system and circuit. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:284-287 [Conf]
- Armin Tajalli, Seyed Mojtaba Atarodi, Abbas Khodaverdi, Farzad Sahandi Esfanjani
Design and optimization of a high PSRR CMOS bandgap voltage reference. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:45-48 [Conf]
- Armin Tajalli, Saeid Mehrmanesh, Seyed Mojtaba Atarodi
A duty cycle control circuit for high speed applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:781-784 [Conf]
- Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. [Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2255-2258 [Conf]
- Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2005, pp:5031-5034 [Conf]
- P. H. Shanjani, Seyed Mojtaba Atarodi
A high dynamic-range, self-tuned Gm-C filter for video-range applications. [Citation Graph (0, 0)][DBLP] ISCAS (2), 1999, pp:660-663 [Conf]
- Saeid Mehrmanesh, Seyed Mojtaba Atarodi
A high dynamic range CMOS variable gain filter for ADSL. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:257-260 [Conf]
- M. B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi
A low-power subscriber line interface circuit in a high-voltage CMOS technology. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:409-412 [Conf]
- Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
A low-power, multichannel gated oscillator-based CDR for short-haul applications. [Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:107-110 [Conf]
- R. Dehghani, Seyed Mojtaba Atarodi, B. Bornoosh, Ali Afzali-Kusha
A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:615-618 [Conf]
- Mostafa Savadi Oskooei, Ali Afzali-Kusha, Seyed Mojtaba Atarodi
A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-µm CMOS Process. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:933-936 [Conf]
- Saeed Sarhangian, Seyed Mojtaba Atarodi
A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee Standard. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:433-436 [Conf]
- Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli
A Power Optimized Base-Band Circuitry for the Low-IF Receivers. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1693-1696 [Conf]
- Mohsen Maadani, Seyed Mojtaba Atarodi
A Low-Area, 0.18µm CMOS, 10Gb/s Optical Receiver Analog Front End. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:3904-3907 [Conf]
- Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- M. Saffari, Seyed Mojtaba Atarodi, Armin Tajalli
A 1/4 rate linear phase detector for PLL-based CDR circuits. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi
A technique to suppress tail current flicker noise in CMOS LC VCOs. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Saeid Mehrmanesh, B. Eghbalkhah, Saeed Saeedi, Ali Afzali-Kusha, Seyed Mojtaba Atarodi
A compact low power mixed-signal equalizer for gigabit Ethernet applications. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal]
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