The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Jeng-Liang Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1168-1171 [Conf]
  2. Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:941-946 [Conf]
  3. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Thermal and Power Integrity Based Power/Ground Networks Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:830-835 [Conf]
  4. Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
    HiSIM: hierarchical interconnect-centric circuit simulator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:489-496 [Conf]
  5. Jeng-Liang Tsai, Lizheng Zhang
    Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:575-581 [Conf]
  6. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    A yield improvement methodology using pre- and post-silicon statistical clock scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:611-618 [Conf]
  7. Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:166-173 [Conf]
  8. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Sensitivity guided net weighting for placement driven synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:124-131 [Conf]
  9. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    False Path and Clock Scheduling Based Yield-Aware Gate Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:423-426 [Conf]
  10. Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
    Yield-Driven, False-Path-Aware Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:214-222 [Journal]
  11. Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
    Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:565-572 [Journal]
  12. Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

Search in 0.031secs, Finished in 0.032secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002