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Publications of Author

1. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
   A General Purpose Multiple Way Partitioning Algorithm. [Citation Graph (2, 0)][DBLP]
   DAC, 1991, pp:421-426 [Conf]
   
2. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
   Performance driven multiple-source bus synthesis using buffer insertion. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
   New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:395-400 [Conf]
   
4. Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng
   Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:274-279 [Conf]
   
5. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
   Simultaneous Routing and Buffer Insertion for High Performance Interconnect. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1996, pp:148-153 [Conf]
   
6. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
   Optimal wire sizing and buffer insertion for low power and a generalized delay model. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:138-143 [Conf]
   
7. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
   A probabilistic multicommodity-flow solution to circuit clustering problems. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1992, pp:428-431 [Conf]
   
8. Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin
   Delay Analysis in Synchronous Circuit-Switched Delta Networks. [Citation Graph (0, 0)][DBLP]
   IPPS, 1993, pp:666-670 [Conf]
   
9. Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
   Optimization of power dissipation and skew sensitivity in clock buffer synthesis. [Citation Graph (0, 0)][DBLP]
   ISLPD, 1995, pp:179-184 [Conf]
   
10. Ting-Ting Y. Lin, Huoy-Yu Liou
    A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:38-51 [Journal]
    
11. Zhiyu Tian, Ting-Ting Y. Lin, Shiyuan Yang, Shibai Tong
    The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction. [Citation Graph (0, 0)][DBLP]
    Neural Computation, 1997, v:9, n:5, pp:1109-1126 [Journal]
    
12. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    A general purpose, multiple-way partitioning algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1480-1488 [Journal]
    
13. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimization by iterative improvement: an experimental evaluation on two-way partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:145-153 [Journal]
    
14. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Circuit clustering using a stochastic flow injection method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:154-162 [Journal]