The SCEAS System
Navigation Menu

Search the dblp DataBase


Akira Tsuchiya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Representative frequency for interconnect R(f)L(f)C extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:691-696 [Conf]
  2. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Return path selection for loop RL extraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1078-1081 [Conf]
  3. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
    Interconnect RL extraction at a single representative frequency. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:515-520 [Conf]
  4. Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    Worst-case delay analysis considering the variability of transistors and interconnects. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:35-42 [Conf]

  5. A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. [Citation Graph (, )][DBLP]

  6. Statistical gate delay model for Multiple Input Switching. [Citation Graph (, )][DBLP]

  7. High performance on-chip differential signaling using passive compensation for global communication. [Citation Graph (, )][DBLP]

  8. On-chip high performance signaling using passive compensation. [Citation Graph (, )][DBLP]

  9. Erect of regularity-enhanced layout on printability and circuit performance of standard cells. [Citation Graph (, )][DBLP]

Search in 0.028secs, Finished in 0.028secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002