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Huy Nam Nguyen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. J. P. Tual, M. Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet
    Auriga2: a 4.7 million-transistor CISC microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
    Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:300-310 [Conf]
  3. Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet
    Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:60-64 [Conf]
  4. Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet
    The Structured Logic CAD Suite Used on the DPS7000 System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:464-467 [Conf]
  5. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
    Designing On-Chip Network Based on Optimal Latency Criteria. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:287-298 [Conf]
  6. Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
    Realization of Video Object Plane Decoder on On-Chip Network Architecture. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:256-264 [Conf]
  7. Vu-Duc Ngo, Huy Nam Nguyen, YoungHwan Bae, HanJin Cho, Hae-Wook Choi
    Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:791-802 [Conf]
  8. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
    The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. [Citation Graph (0, 0)][DBLP]
    ISPA, 2006, pp:75-85 [Conf]
  9. Huy Nam Nguyen, L. Ducousso
    Automated synthesis of combinational logic using problem solving techniques. [Citation Graph (0, 0)][DBLP]
    SPLT, 1989, pp:577-582 [Conf]
  10. Huy Nam Nguyen, L. Ducousso
    Utilisation de CHIP pour la synthèse et vérification des circuits CMOS. [Citation Graph (0, 0)][DBLP]
    SPLT, 1988, pp:267-278 [Conf]
  11. Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
    Realization of video object plane decoder on mesh on-chip network architecture. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2005, pp:137-141 [Conf]
  12. Huy Nam Nguyen, Vu-Duc Ngo, YoungHwan Bae, HanJin Cho, Hae-Wook Choi
    An QoS Aware Mapping of Cores Onto NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISPA, 2007, pp:278-288 [Conf]

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