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Magdy S. Abadir: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
    Design rewiring based on diagnosis techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:479-484 [Conf]
  2. Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu
    Automated Test Model Generation from Switch Level Custom Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:184-189 [Conf]
  3. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
    Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:386-402 [Conf]
  4. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    Analytical models for leakage power estimation of memory array structures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:146-151 [Conf]
  5. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    Floorplan driven leakage power aware IP-based SoC design space exploration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:118-123 [Conf]
  6. Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
    Refined statistical static timing analysis through. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:149-154 [Conf]
  7. Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir
    Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:167-172 [Conf]
  8. Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir
    Automatic Test Knowledge Extraction from VHDL (ATKET). [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:273-278 [Conf]
  9. Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy
    Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:534-537 [Conf]
  10. Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
    On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:492-497 [Conf]
  11. Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
    Choosing flows and methodologies for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:167- [Conf]
  12. Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
    False timing path identification using ATPG techniques and delay-based information. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:562-565 [Conf]
  13. A. J. van de Goor, Magdy S. Abadir, Alan Carlin
    Minimal Test for Coupling Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:944-948 [Conf]
  14. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
  15. Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
    Incremental Diagnosis and Correction of Multiple Faults and Errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:716-721 [Conf]
  16. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:273-277 [Conf]
  17. Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
    Full chip false timing path identification: applications to the PowerPCTM microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:514-519 [Conf]
  18. James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Efficient Algorithmic Circuit Verification Using Indexed BDDs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:266-275 [Conf]
  19. Arun Chandra, Li-C. Wang, Magdy S. Abadir
    Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:362-367 [Conf]
  20. Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
    Diagnosing multiple transition faults in the absence of timing information. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:193-196 [Conf]
  21. Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir
    Extracting a Simplified View of Design Functionality Based on Vector Simulation. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:34-49 [Conf]
  22. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:871-876 [Conf]
  23. Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
    Debugging sequential circuits using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:204-209 [Conf]
  24. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    IDAP: A Tool for High Level Power Estimation of Custom Array Structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:113-119 [Conf]
  25. Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
    AMBIANT: Automatic Generation of Behavioral Modifications for Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:63-66 [Conf]
  26. Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir
    Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:65-0 [Conf]
  27. Magdy S. Abadir
    Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:81- [Conf]
  28. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri
    Fault equivalence and diagnostic test generation using ATPG. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:221-224 [Conf]
  29. Magdy S. Abadir, Li-C. Wang
    Verification and Validation of Complex Digital Systems: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:11-12 [Conf]
  30. Magdy S. Abadir, Melvin A. Breuer
    Scan Path with Look Ahead Shifting (SPLASH). [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:696-704 [Conf]
  31. Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer
    Partitioning Hierarchical Designs for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:174-183 [Conf]
  32. Magdy S. Abadir, Hassan K. Reghbati
    Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:483-492 [Conf]
  33. Magdy S. Abadir, Rajesh Raina
    Design-for-test methodology for Motorola PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:810-819 [Conf]
  34. Neeta Ganguly, Magdy S. Abadir, Manish Pandey
    PowerPCTM Array Verification Methodology using Formal Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:857-864 [Conf]
  35. Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
    Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:203-212 [Conf]
  36. Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
    Design Rewiring Using ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:223-232 [Conf]
  37. Li-C. Wang, Magdy S. Abadir
    A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:954-963 [Conf]
  38. Li-C. Wang, Magdy S. Abadir
    Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:830-838 [Conf]
  39. Li-C. Wang, Magdy S. Abadir, Juhong Zhu
    On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:398-406 [Conf]
  40. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  41. Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:31-37 [Conf]
  42. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-Verification Debugging of Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:42-47 [Conf]
  43. Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith
    Debugging Sequential Circuits Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:44-49 [Conf]
  44. Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova
    Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:111-118 [Conf]
  45. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
    A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:32-37 [Conf]
  46. Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
    Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:33-36 [Conf]
  47. Brian Kahne, Magdy S. Abadir
    Retiming Verification Using Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:138-142 [Conf]
  48. M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
    Identification of Gates for Covering all Critical Paths. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:92-96 [Conf]
  49. Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:103-109 [Conf]
  50. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Towards The Complete Elimination of Gate/Switch Level Simulations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:115-0 [Conf]
  51. Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea
    Recent Advances in Verification, Equivalence Checking and SAT-Solvers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:14- [Conf]
  52. Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
    STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:559-564 [Conf]
  53. Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther
    Microprocessor Test and Validation: Any New Avenues? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:458-464 [Conf]
  54. Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
    ATPG for Design Errors-Is It Possible? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:283-285 [Conf]
  55. Magdy S. Abadir, Juhong Zhu
    Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:22-30 [Conf]
  56. Magdy S. Abadir, Juhong Zhu, Li-C. Wang
    Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:252-259 [Conf]
  57. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:275-280 [Conf]
  58. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
    Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:9-14 [Conf]
  59. Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
    Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:153-160 [Conf]
  60. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:260-265 [Conf]
  61. Magdy S. Abadir, Hassan K. Reghbati
    Functional Testing of Semiconductor Random Access Memories. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1983, v:15, n:3, pp:175-198 [Journal]
  62. Magdy S. Abadir, Sumit DasGupta
    Guest Editors' Introduction: Microprocessor Test and Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:4-5 [Journal]
  63. Magdy S. Abadir, Rohit Kapur
    Cost-Driven Ranking of Memory Elements for Partial Intrusion. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:3, pp:45-50 [Journal]
  64. Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake
    Analyzing Multichip Module Testing Strategies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:1, pp:40-52 [Journal]
  65. Magdy S. Abadir, Li-C. Wang
    Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:80-82 [Journal]
  66. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
    Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:494-502 [Journal]
  67. Tony Ambler, Magdy S. Abadir
    Design and Test Economics-An Extra Dimension. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:3, pp:15-16 [Journal]
  68. Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir
    Very Low Cost Testers: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:60-69 [Journal]
  69. Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
    Design and Development Paradigm for Industrial Formal Verification CAD Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:26-35 [Journal]
  70. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
    Validating PowerPC Microprocessor Custom Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:61-76 [Journal]
  71. Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
    A Top-Down Methodology for Microprocessor Validation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:122-131 [Journal]
  72. Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin
    Formal Verification Successes at Motorola. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:2, pp:117-123 [Journal]
  73. Magdy S. Abadir, Melvin A. Breuer
    Test Schedules for VLSI Circuits Having Built-In Test Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:361-367 [Journal]
  74. Magdy S. Abadir, Hassan K. Reghbati
    Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:375-379 [Journal]
  75. Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1230-1245 [Journal]
  76. Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland
    Logic design verification via test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:138-148 [Journal]
  77. Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
    IDAP: a tool for high-level power estimation of custom array structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1361-1369 [Journal]
  78. Andreas G. Veneris, Magdy S. Abadir
    Design rewiring using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1469-1479 [Journal]
  79. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:524-532 [Journal]
  80. Li-C. Wang, Pouria Bastani, Magdy S. Abadir
    Design-Silicon Timing Correlation A Data Mining Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:384-389 [Conf]
  81. Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
    Maximum circuit activity estimation using pseudo-boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1538-1543 [Conf]
  82. Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi
    Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:495-502 [Journal]

  83. LEAF: A System Level Leakage-Aware Floorplanner for SoCs. [Citation Graph (, )][DBLP]


  84. Statistical diagnosis of unmodeled systematic timing effects. [Citation Graph (, )][DBLP]


  85. Predictive runtime verification of multi-processor SoCs in SystemC. [Citation Graph (, )][DBLP]


  86. Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. [Citation Graph (, )][DBLP]


  87. TRAM: A tool for Temperature and Reliability Aware Memory Design. [Citation Graph (, )][DBLP]


  88. An improved layout verification algorithm (LAVA). [Citation Graph (, )][DBLP]


  89. Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. [Citation Graph (, )][DBLP]


  90. A Survey of Hybrid Techniques for Functional Verification. [Citation Graph (, )][DBLP]


  91. Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. [Citation Graph (, )][DBLP]


  92. Linking Statistical Learning to Diagnosis. [Citation Graph (, )][DBLP]


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