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Ganesh Venkataraman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
    Skew scheduling and clock routing for improved tolerance to process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:594-599 [Conf]
  2. Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
    Integrated placement and skew optimization for rotary clocking. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:756-761 [Conf]
  3. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
    Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:592-596 [Conf]
  4. Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra
    DiCER: distributed and cost-effective redundancy for variation tolerance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:393-397 [Conf]
  5. Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
    Combinatorial algorithms for fast clock mesh optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:563-567 [Conf]
  6. Rupak Samanta, Ganesh Venkataraman, Jiang Hu
    Clock buffer polarity assignment for power noise reduction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:558-562 [Conf]
  7. Kasturi R. Varadarajan, Ganesh Venkataraman
    Graph decomposition and a greedy algorithm for edge-disjoint paths. [Citation Graph (0, 0)][DBLP]
    SODA, 2004, pp:379-380 [Conf]
  8. Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz
    GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:533-538 [Conf]
  9. Ganesh Venkataraman, Jiang Hu
    A Placement Methodology for Robust Clocking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:881-886 [Conf]
  10. Ganesh Venkataraman, Jiang Hu, Frank Liu
    Integrated Placement and Skew Optimization for Rotary Clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:149-158 [Journal]

  11. A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. [Citation Graph (, )][DBLP]


  12. Elastic Timing Scheme for Energy-Efficient and Robust Performance. [Citation Graph (, )][DBLP]


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