SCEAS

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Ian G. Harris: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Shireesh Verma, Kiran Ramineni, Ian G. Harris
An efficient control-oriented coverage metric. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2005, pp:317-322 [Conf]
Ian G. Harris, Alex Orailoglu
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. [Citation Graph (0, 0)][DBLP]
DAC, 1994, pp:206-211 [Conf]
Ian G. Harris, Russell Tessier
Interconnect testing in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
DAC, 2000, pp:49-54 [Conf]
Ian G. Harris
A coverage metric for the validation of interacting processes. [Citation Graph (0, 0)][DBLP]
DATE, 2006, pp:1019-1024 [Conf]
Matthew W. Heath, Wayne P. Burleson, Ian G. Harris
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. [Citation Graph (0, 0)][DBLP]
DATE, 2004, pp:410-415 [Conf]
Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski
Fast Computation of Data Correlation Using BDDs. [Citation Graph (0, 0)][DBLP]
DATE, 2003, pp:10122-10129 [Conf]
Ian G. Harris, Alex Orailoglu
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. [Citation Graph (0, 0)][DBLP]
EDAC-ETC-EUROASIC, 1994, pp:119-123 [Conf]
Ian G. Harris, Russell Tessier
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. [Citation Graph (0, 0)][DBLP]
ICCAD, 2000, pp:472-475 [Conf]
Qiushuang Zhang, Ian G. Harris
A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. [Citation Graph (0, 0)][DBLP]
ICCAD, 2000, pp:369-372 [Conf]
Qiushuang Zhang, Ian G. Harris
Partial BIST insertion to eliminate data correlation. [Citation Graph (0, 0)][DBLP]
ICCAD, 1999, pp:395-399 [Conf]
Ian G. Harris, Alex Orailoglu
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. [Citation Graph (0, 0)][DBLP]
ICCD, 1994, pp:101-104 [Conf]
Alex Orailoglu, Ian G. Harris
Test Path Generation and Test Scheduling for Self-Testable Designs. [Citation Graph (0, 0)][DBLP]
ICCD, 1993, pp:528-531 [Conf]
Ian G. Harris, Alex Orailoglu
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. [Citation Graph (0, 0)][DBLP]
ISCAS, 1993, pp:1682-1685 [Conf]
Dereck A. Fernandes, Ian G. Harris
Application of Built in Self-Test for Interconnect Testing of FPGAs. [Citation Graph (0, 0)][DBLP]
ITC, 2003, pp:1248-1257 [Conf]
Ian G. Harris
The Confluence of Manufacturing Test and Design Validation. [Citation Graph (0, 0)][DBLP]
ITC, 2003, pp:1290- [Conf]
Ian G. Harris, Premachandran R. Menon, Russell Tessier
BIST-based delay path testing in FPGA architectures. [Citation Graph (0, 0)][DBLP]
ITC, 2001, pp:932-938 [Conf]
Qiushuang Zhang, Ian G. Harris
A domain coverage metric for the validation of behavioral VHDL descriptions. [Citation Graph (0, 0)][DBLP]
ITC, 2000, pp:302-308 [Conf]
Qiushuang Zhang, Ian G. Harris
A validation fault model for timing-induced functional errors. [Citation Graph (0, 0)][DBLP]
ITC, 2001, pp:813-820 [Conf]
Matthew W. Heath, Ian G. Harris
A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. [Citation Graph (0, 0)][DBLP]
MTV, 2003, pp:119-0 [Conf]
P. Venkat Rangan, Walter A. Burkhard, Robert W. Rowdidge, Harrick M. Vin, John W. Lindwall, Kashun Chan, Ingvar A. Aaberg, Linda M. Yamamoto, Ian G. Harris
A Testbed for Managing Digital Video and Audio Storage. [Citation Graph (0, 0)][DBLP]
USENIX Summer, 1991, pp:199-208 [Conf]
Ian G. Harris
Fault Models and Test Generation for Hardware-Software Covalidation. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2003, v:20, n:4, pp:40-47 [Journal]
Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken
ITC 2003 panels: Part 1. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2004, v:21, n:2, pp:160-163 [Journal]
Franco Fummi, Ian G. Harris
Editorial. [Citation Graph (0, 0)][DBLP]
International Journal of Parallel Programming, 2005, v:33, n:6, pp:583-584 [Journal]
Ian G. Harris, Franco Fummi
Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
International Journal of Parallel Programming, 2006, v:34, n:1, pp:1-2 [Journal]
Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris
ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. [Citation Graph (0, 0)][DBLP]
Journal of Circuits, Systems, and Computers, 2003, v:12, n:3, pp:305-332 [Journal]
Ian G. Harris
Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2006, v:55, n:11, pp:1313-1314 [Journal]
Matthew W. Heath, Wayne P. Burleson, Ian G. Harris
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2005, v:54, n:12, pp:1532-1546 [Journal]
Ian G. Harris, Russell Tessier
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1337-1343 [Journal]
Qiushuang Zhang, Ian G. Harris
Partial BIST insertion to eliminate data correlation. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:374-379 [Journal]
Ian G. Harris
Introduction. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:587-588 [Journal]
Shireesh Verma, Ian G. Harris, Kiran Ramineni
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. [Citation Graph (0, 0)][DBLP]
DATE, 2007, pp:900-905 [Conf]
A CLP-Based Functional ATPG for Extended FSMs. [Citation Graph (, )][DBLP]

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