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Mário P. Véstias: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mário P. Véstias, Horácio C. Neto
    Co-synthesis of a configurable SoC platform based on a network on chip architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:48-53 [Conf]
  2. Mário P. Véstias, Horácio C. Neto
    System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:130-137 [Conf]
  3. Mário P. Véstias, Horácio C. Neto
    Area and performance optimization of a generic network-on-chip architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:68-73 [Conf]
  4. Mário P. Véstias, Horácio C. Neto
    DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:85-0 [Conf]
  5. Mário P. Véstias, Horácio C. Neto
    A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  6. Mário P. Véstias, Horácio C. Neto
    Area/Performance Improvement of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:193-198 [Conf]

  7. Run-Time Reconfigurable Array Using Magnetic RAM. [Citation Graph (, )][DBLP]

  8. Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. [Citation Graph (, )][DBLP]

  9. Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]

  10. Decimal multiplier on FPGA using embedded binary multipliers. [Citation Graph (, )][DBLP]

  11. Multiplier-based double precision floating point divider according to the IEEE-754 standard. [Citation Graph (, )][DBLP]

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