The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Horácio C. Neto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mário P. Véstias, Horácio C. Neto
    Co-synthesis of a configurable SoC platform based on a network on chip architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:48-53 [Conf]
  2. João M. P. Cardoso, Horácio C. Neto
    Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:2-11 [Conf]
  3. João M. P. Cardoso, Horácio C. Neto
    Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:523-533 [Conf]
  4. Pedro Domingos, Fernando M. Silva, Horácio C. Neto
    An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:89-94 [Conf]
  5. Ricardo Ferreira, João M. P. Cardoso, Horácio C. Neto
    An Environment for Exploring Data-Driven Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1022-1026 [Conf]
  6. Paulo F. Flores, Horácio C. Neto, João P. Marques Silva
    On Applying Set Covering Models to Test Set Compaction. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:8-11 [Conf]
  7. João M. P. Cardoso, Horácio C. Neto
    An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:485-496 [Conf]
  8. Paulo F. Flores, Horácio C. Neto, K. Chakrabarty, João P. Marques Silva
    Test pattern generation for width compression in BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:114-118 [Conf]
  9. Mário P. Véstias, Horácio C. Neto
    System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:130-137 [Conf]
  10. Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto
    Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:41-50 [Conf]
  11. Mário P. Véstias, Horácio C. Neto
    Area and performance optimization of a generic network-on-chip architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:68-73 [Conf]
  12. Mário P. Véstias, Horácio C. Neto
    DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:85-0 [Conf]
  13. Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva
    Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:37-41 [Conf]
  14. José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
    Bitwise Encoding of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:379-382 [Conf]
  15. João M. P. Cardoso, Horácio C. Neto
    Compilation for FPGA-Based Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:65-75 [Journal]
  16. Luis Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal
    On exponential fitting for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:566-574 [Journal]
  17. Paulo F. Flores, Horácio C. Neto, João P. Marques Silva
    An exact solution to the minimum size test pattern problem. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:629-644 [Journal]
  18. Mário P. Véstias, Horácio C. Neto
    A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  19. Goncalo M. de Matos, Horácio C. Neto
    On Reconfigurable Architectures for Efficient Matrix Inversion. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  20. Mário P. Véstias, Horácio C. Neto
    Area/Performance Improvement of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:193-198 [Conf]

  21. Run-Time Reconfigurable Array Using Magnetic RAM. [Citation Graph (, )][DBLP]


  22. Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. [Citation Graph (, )][DBLP]


  23. Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. [Citation Graph (, )][DBLP]


  24. Decimal multiplier on FPGA using embedded binary multipliers. [Citation Graph (, )][DBLP]


  25. Sorting Units for FPGA-Based Embedded Systems. [Citation Graph (, )][DBLP]


  26. Reconfigurable Circuits Using Magnetic Tunneling Junction Memories. [Citation Graph (, )][DBLP]


  27. Multiplier-based double precision floating point divider according to the IEEE-754 standard. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.006secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002