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Kedarnath J. Balakrishnan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan
    Re-configurable embedded core test protocol. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:234-237 [Conf]
  2. Kedarnath J. Balakrishnan
    Emerging Techniques for Test Data Compression. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:462- [Conf]
  3. Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
    Compressing Functional Tests for Microprocessors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:428-433 [Conf]
  4. Kedarnath J. Balakrishnan, Nur A. Touba
    Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1130-1135 [Conf]
  5. Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar
    Efficient unknown blocking using LFSR reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1051-1052 [Conf]
  6. Kedarnath J. Balakrishnan, Nur A. Touba
    Matrix-Based Test Vector Decompression Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:159-165 [Conf]
  7. Kedarnath J. Balakrishnan, Nur A. Touba
    Scan-Based BIST Diagnosis Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:209-216 [Conf]
  8. Kedarnath J. Balakrishnan, Nur A. Touba
    Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:936-944 [Conf]
  9. Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar
    PIDISC: Pattern Independent Design Independent Seed Compression Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:811-817 [Conf]
  10. Kedarnath J. Balakrishnan
    Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:345-350 [Conf]
  11. Kedarnath J. Balakrishnan, Nur A. Touba
    Deterministic Test Vector Decompression in Software Using Linear Operations. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:225-231 [Conf]
  12. Kedarnath J. Balakrishnan, Lei Fang
    RTL Test Point Insertion to Reduce Delay Test Volume. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:325-332 [Conf]
  13. Kedarnath J. Balakrishnan, Nur A. Touba
    Matrix-based software test data decompression for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:247-256 [Journal]
  14. Quming Zhou, Kedarnath J. Balakrishnan
    Test cost reduction for SoC using a combined approach to test data compression and test scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:39-44 [Conf]
  15. Kedarnath J. Balakrishnan, Nur A. Touba
    Improving Linear Test Data Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1227-1237 [Journal]

  16. Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor. [Citation Graph (, )][DBLP]


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