The SCEAS System
Navigation Menu

Search the dblp DataBase


Renshen Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Renshen Wang, Sheqin Dong, Xianlong Hong
    An improved P-admissible floorplan representation based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1115-1118 [Conf]
  2. Renshen Wang, Rui Shi, Chung-Kuan Cheng
    Layer minimization of escape routing in area array packaging. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:815-819 [Conf]

  3. Noise minimization during power-up stage for a multi-domain power network. [Citation Graph (, )][DBLP]

  4. Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. [Citation Graph (, )][DBLP]

  5. On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. [Citation Graph (, )][DBLP]

  6. Octilinear redistributive routing in bump arrays. [Citation Graph (, )][DBLP]

  7. Low Power Passive Equalizer Design for Computer Memory Links. [Citation Graph (, )][DBLP]

  8. 3-D floorplanning using labeled tree and dual sequences. [Citation Graph (, )][DBLP]

  9. Physical synthesis of bus matrix for high bandwidth low power on-chip communications. [Citation Graph (, )][DBLP]

Search in 0.015secs, Finished in 0.015secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002