The SCEAS System
Navigation Menu

Search the dblp DataBase


Lars Hedrich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaoying Wang, Lars Hedrich
    An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:700-705 [Conf]
  2. Walter Hartong, Lars Hedrich, Erich Barke
    On Discrete Modeling and Model Checking for Nonlinear Analog Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:401-413 [Conf]
  3. Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
    A current driven routing and verification methodology for analog applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:385-389 [Conf]
  4. Carsten Borchers, Lars Hedrich, Erich Barke
    Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:236-239 [Conf]
  5. Walter Hartong, Lars Hedrich, Erich Barke
    Model checking algorithms for analog verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:542-547 [Conf]
  6. Walter Hartong, Lars Hedrich, Erich Barke
    An Approach to Model Checking for Nonlinear Analog Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1080- [Conf]
  7. Lars Hedrich, Erich Barke
    A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:649-0 [Conf]
  8. Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
    Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:442-447 [Conf]
  9. Rolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
    Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:274-278 [Conf]
  10. Lars Hedrich, Erich Barke
    A formal approach to nonlinear analog circuit verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:123-127 [Conf]
  11. Andreas C. Lemke, Lars Hedrich, Erich Barke
    Analog circuit sizing based on formal methods using affine arithmetic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:486-489 [Conf]
  12. Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
    Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:37-52 [Journal]
  13. Xiaoying Wang, Lars Hedrich
    Hierarchical exploration and selection of transistor-topologies for analog circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  14. A symbolic approach for mixed-signal model checking. [Citation Graph (, )][DBLP]

  15. Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. [Citation Graph (, )][DBLP]

  16. Model Checking of Analog Systems using an Analog Specification Language. [Citation Graph (, )][DBLP]

  17. Formal approaches to analog circuit verification. [Citation Graph (, )][DBLP]

  18. Towards assertion-based verification of heterogeneous system designs. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.002secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002