The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

John Lillis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal
    An LP-based methodology for improved timing-driven placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1139-1143 [Conf]
  2. Giancarlo Beraudo, John Lillis
    Timing optimization of FPGA placements by logic replication. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:196-201 [Conf]
  3. Milos Hrkic, John Lillis
    S-Tree: a technique for buffered routing tree synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:578-583 [Conf]
  4. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An approach to placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:711-716 [Conf]
  5. Sung-Woo Hur, John Lillis
    Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:360-366 [Conf]
  6. Ashok Jagannathan, Sung-Woo Hur, John Lillis
    A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:368-373 [Conf]
  7. Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng
    New Spectral Linear Placement and Clustering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:88-93 [Conf]
  8. John Lillis, Premal Buch
    Table-Lookup Methods for Improved Performance-Driven Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:368-373 [Conf]
  9. John Lillis, Chung-Kuan Cheng
    Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:214-219 [Conf]
  10. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
    New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:395-400 [Conf]
  11. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Simultaneous Routing and Buffer Insertion for High Performance Interconnect. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:148-153 [Conf]
  12. Hosung (Leo) Kim, John Lillis, Milos Hrkic
    Techniques for improved placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:211-216 [Conf]
  13. Qingzhou (Ben) Wang, Devang Jariwala, John Lillis
    A study of tighter lower bounds in LP relaxation based placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:498-502 [Conf]
  14. Sung-Woo Hur, John Lillis
    MONGREL: Hybrid Techniques for Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:165-170 [Conf]
  15. Devang Jariwala, John Lillis
    On interactions between routing and detailed placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:387-393 [Conf]
  16. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
    Optimal wire sizing and buffer insertion for low power and a generalized delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:138-143 [Conf]
  17. Jianmin Li, John Lillis, Chung-Kuan Cheng
    Linear decomposition algorithm for VLSI design applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:223-228 [Conf]
  18. Devang Jariwala, John Lillis
    Trunk decomposition based global routing optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:472-479 [Conf]
  19. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  20. Milos Hrkic, John Lillis
    Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:98-103 [Conf]
  21. Sung-Woo Hur, Ashok Jagannathan, John Lillis
    Timing driven maze routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:208-213 [Conf]
  22. Milos Hrkic, John Lillis
    Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:481-491 [Journal]
  23. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An Approach to Placement-Coupled Logic Replication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2539-2551 [Journal]
  24. Sung-Woo Hur, Ashok Jagannathan, John Lillis
    Timing-driven maze routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:234-241 [Journal]
  25. John Lillis, Chung-Kuan Cheng
    Timing optimization for multisource nets: characterization andoptimal repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:322-331 [Journal]
  26. Ashok Jagannathan, Sung-Woo Hur, John Lillis
    A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:173-188 [Journal]
  27. Salim Chowdhury, John Lillis
    Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:59-66 [Conf]

  28. Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. [Citation Graph (, )][DBLP]


  29. A framework for layout-level logic restructuring. [Citation Graph (, )][DBLP]


Search in 0.478secs, Finished in 0.481secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002