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John Lillis :
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Qingzhou (Ben) Wang , John Lillis , Shubhankar Sanyal An LP-based methodology for improved timing-driven placement. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1139-1143 [Conf ] Giancarlo Beraudo , John Lillis Timing optimization of FPGA placements by logic replication. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:196-201 [Conf ] Milos Hrkic , John Lillis S-Tree: a technique for buffered routing tree synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:578-583 [Conf ] Milos Hrkic , John Lillis , Giancarlo Beraudo An approach to placement-coupled logic replication. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:711-716 [Conf ] Sung-Woo Hur , John Lillis Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:360-366 [Conf ] Ashok Jagannathan , Sung-Woo Hur , John Lillis A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:368-373 [Conf ] Jianmin Li , John Lillis , Lung-Tien Liu , Chung-Kuan Cheng New Spectral Linear Placement and Clustering Approach. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:88-93 [Conf ] John Lillis , Premal Buch Table-Lookup Methods for Improved Performance-Driven Routing. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:368-373 [Conf ] John Lillis , Chung-Kuan Cheng Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:214-219 [Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin , Chin-Yen Ho New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:395-400 [Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin Simultaneous Routing and Buffer Insertion for High Performance Interconnect. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:148-153 [Conf ] Hosung (Leo) Kim , John Lillis , Milos Hrkic Techniques for improved placement-coupled logic replication. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:211-216 [Conf ] Qingzhou (Ben) Wang , Devang Jariwala , John Lillis A study of tighter lower bounds in LP relaxation based placement. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:498-502 [Conf ] Sung-Woo Hur , John Lillis MONGREL: Hybrid Techniques for Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:165-170 [Conf ] Devang Jariwala , John Lillis On interactions between routing and detailed placement. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:387-393 [Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin Optimal wire sizing and buffer insertion for low power and a generalized delay model. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:138-143 [Conf ] Jianmin Li , John Lillis , Chung-Kuan Cheng Linear decomposition algorithm for VLSI design applications. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:223-228 [Conf ] Devang Jariwala , John Lillis Trunk decomposition based global routing optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:472-479 [Conf ] Charles J. Alpert , Milos Hrkic , Jiang Hu , Andrew B. Kahng , John Lillis , Bao Liu , Stephen T. Quay , Sachin S. Sapatnekar , A. J. Sullivan , Paul Villarrubia Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP ] ISPD, 2001, pp:4-9 [Conf ] Milos Hrkic , John Lillis Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. [Citation Graph (0, 0)][DBLP ] ISPD, 2002, pp:98-103 [Conf ] Sung-Woo Hur , Ashok Jagannathan , John Lillis Timing driven maze routing. [Citation Graph (0, 0)][DBLP ] ISPD, 1999, pp:208-213 [Conf ] Milos Hrkic , John Lillis Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:481-491 [Journal ] Milos Hrkic , John Lillis , Giancarlo Beraudo An Approach to Placement-Coupled Logic Replication. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2539-2551 [Journal ] Sung-Woo Hur , Ashok Jagannathan , John Lillis Timing-driven maze routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:234-241 [Journal ] John Lillis , Chung-Kuan Cheng Timing optimization for multisource nets: characterization andoptimal repeater insertion. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:322-331 [Journal ] Ashok Jagannathan , Sung-Woo Hur , John Lillis A fast algorithm for context-aware buffer insertion. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:173-188 [Journal ] Salim Chowdhury , John Lillis Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. [Citation Graph (0, 0)][DBLP ] ISPD, 2007, pp:59-66 [Conf ] Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. [Citation Graph (, )][DBLP ] A framework for layout-level logic restructuring. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.304secs