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Ganesh Lakshminarayana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:711-718 [Conf]
  2. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-Software Co-Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:703-708 [Conf]
  3. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Power analysis of embedded operating systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:312-315 [Conf]
  4. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:15-20 [Conf]
  5. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:513-518 [Conf]
  6. Ganesh Lakshminarayana, Niraj K. Jha
    FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:102-107 [Conf]
  7. Ganesh Lakshminarayana, Niraj K. Jha
    Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:439-444 [Conf]
  8. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:108-113 [Conf]
  9. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  10. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level Software Energy Macro-modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:605-610 [Conf]
  11. W. Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:738-743 [Conf]
  12. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:848-854 [Conf]
  13. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:336-345 [Conf]
  14. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:482-488 [Conf]
  15. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:244-250 [Conf]
  16. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:657-664 [Conf]
  17. Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
    Transient Power Management Through High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:545-552 [Conf]
  18. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:577-584 [Conf]
  19. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    A framework for testing core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:385-390 [Conf]
  20. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Fast high-level power estimation for control-flow intensive design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:299-304 [Conf]
  21. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    : Reducing test application time in high-level test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:829-838 [Conf]
  22. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression based high-level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:331-340 [Conf]
  23. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    A Power Management Methodology for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:24-19 [Conf]
  24. Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
    Accurate Power Macro-modeling Techniques for Complex RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:235-241 [Conf]
  25. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
    High-Level Synthesis with Variable-Latency Components. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:220-227 [Conf]
  26. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:711-718 [Conf]
  27. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:398-406 [Conf]
  28. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:865-885 [Journal]
  29. Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Analysis of power dissipation in embedded systems using real-time operating systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:615-627 [Journal]
  30. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of low-power control-flow intensive circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1715-1729 [Journal]
  31. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Design of high-performance system-on-chips using communication architecture tuners. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:620-636 [Journal]
  32. Ganesh Lakshminarayana, Niraj K. Jha
    High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:265-281 [Journal]
  33. Ganesh Lakshminarayana, Niraj K. Jha
    FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1577-1594 [Journal]
  34. Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha
    Wavesched: a novel scheduling technique for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:505-523 [Journal]
  35. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha
    Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:308-324 [Journal]
  36. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
  37. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
    Integrating variable-latency components into high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1105-1117 [Journal]
  38. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:894-906 [Journal]
  39. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Testing of core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:426-439 [Journal]
  40. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    High-level test compaction techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:827-841 [Journal]
  41. Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    High-level energy macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1037-1050 [Journal]
  42. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space-adaptive optimization for embedded-software synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1677-1693 [Journal]
  43. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
    Memory binding for performance optimization of control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:513-524 [Journal]
  44. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
    Input space adaptive design: a high-level methodology for optimizing energy and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:590-602 [Journal]
  45. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    The LOTTERYBUS on-chip communication architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:596-608 [Journal]
  46. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:92-104 [Journal]
  47. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Power management in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:7-15 [Journal]
  48. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression-based register-transfer level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:824-832 [Journal]

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