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Publications of Author

1. Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov
   A retention-aware test power model for embedded SRAM. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1180-1183 [Conf]
   
2. Yuejian Wu, Sanjay Gupta
   Built-In Self-Test for Multi-Port RAMs. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:398-403 [Conf]
   
3. Baosheng Wang, Yuejian Wu, André Ivanov
   A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:852-857 [Conf]
   
4. Yuejian Wu
   Diagnosis of Scan Chain Failures. [Citation Graph (0, 0)][DBLP]
   DFT, 1998, pp:217-0 [Conf]
   
5. Baosheng Wang, Yuejian Wu, André Ivanov
   Designs for Reducing Test Time of Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
   DFT, 2004, pp:120-128 [Conf]
   
6. Yuejian Wu, André Ivanov
   Low Power SoC Memory BIST. [Citation Graph (0, 0)][DBLP]
   DFT, 2006, pp:197-205 [Conf]
   
7. Yuejian Wu
   Low power decoding of BCH codes. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:369-372 [Conf]
   
8. Yuejian Wu, Saman Adham
   BIST Fault Diagnosis in Scan-Based VLSI Environments. [Citation Graph (0, 0)][DBLP]
   ITC, 1996, pp:48-57 [Conf]
   
9. Yuejian Wu, Liviu Calin
   Shadow write and read for at-speed BIST of TDM SRAMs. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:985-994 [Conf]
   
10. Yuejian Wu, Paul Soong
    Interconnect delay fault testing with IEEE 1149.1. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:449-457 [Conf]
    
11. Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu
    Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:83-0 [Conf]
    
12. Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian
    SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:66-71 [Conf]
    
13. Yuejian Wu, André Ivanov
    Reducing Hardware with Fuzzy Multiple Signature Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:68-74 [Journal]
    
14. Yuejian Wu, André Ivanov
    Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:6, pp:817-825 [Journal]
    
15. Yuejian Wu, Saman Adham
    Scan-based BIST fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:203-211 [Journal]
    
16. Yuejian Wu, Paul N. MacDonald
    Testing ASICs with multiple identical cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:327-336 [Journal]
    
17. Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov
    Fast detection of data retention faults and other SRAM cell open defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:167-180 [Journal]
    
18. Baosheng Wang, Yuejian Wu, André Ivanov
    A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
19. 
    Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC. [Citation Graph (, )][DBLP]