The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
André Ivanov: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov
    A retention-aware test power model for embedded SRAM. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1180-1183 [Conf]
  2. Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
    A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:383-387 [Conf]
  3. Maneesha Dalmia, André Ivanov, Sassan Tabatabaei
    Power supply current monitoring techniques for testing PLLs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:366-371 [Conf]
  4. Vikram Devdas, André Ivanov
    Non-Intrusive Testing of High-Speed CML Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:172-178 [Conf]
  5. Zahra Sadat Ebadi, André Ivanov
    Design of an Optimal Test Access Architecture Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:205-0 [Conf]
  6. Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell
    Testing for Floating Gates Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:228-236 [Conf]
  7. Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov
    Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:348-353 [Conf]
  8. Zahra Sadat Ebadi, André Ivanov
    Time Domain Multiplexed TAM: Implementation and Comparison. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10732-10737 [Conf]
  9. Baosheng Wang, Yuejian Wu, André Ivanov
    A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:852-857 [Conf]
  10. A. J. Bishop, André Ivanov
    On the Testability of CMOS Feedback Amplifiers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:65-73 [Conf]
  11. Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh
    Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:238-246 [Conf]
  12. Baosheng Wang, Yuejian Wu, André Ivanov
    Designs for Reducing Test Time of Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:120-128 [Conf]
  13. Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande
    NoC Interconnect Yield Improvement Using Crosspoint Redundancy. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:457-465 [Conf]
  14. Yuejian Wu, André Ivanov
    Low Power SoC Memory BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:197-205 [Conf]
  15. Yervant Zorian, André Ivanov
    Programmable Space Compaction for BIST. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:340-349 [Conf]
  16. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:192-195 [Conf]
  17. André Ivanov, Yervant Zorian
    Computing the Error Escape Probability in Count-Based Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:368-371 [Conf]
  18. B. Alorda, André Ivanov, Jaume Segura
    An Off-Chip Sensor Circuit for On-Line Transient Current Testing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:192- [Conf]
  19. Ashish Syal, Victor Lee, André Ivanov, Josep Altet
    CMOS Differential and Absolute Thermal Sensors. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:127-0 [Conf]
  20. Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande
    On-line Fault Detection and Location for NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:145-150 [Conf]
  21. Andrew Bishop, André Ivanov
    Fault Simulation of an OTA Biquadratic Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1764-1767 [Conf]
  22. Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov
    Analog IP design flow for SoC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:676-679 [Conf]
  23. Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh
    Design of a switch for network on chip applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:217-220 [Conf]
  24. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh
    Effect of traffic localization on energy dissipation in NoC-based interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1774-1777 [Conf]
  25. Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
    A 0.35µm CMOS comparator circuit for high-speed ADC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6134-6137 [Conf]
  26. Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
    A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6138-6141 [Conf]
  27. Sassan Tabatabaei, André Ivanov
    A built-in current monitor for testing analog circuit blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:109-114 [Conf]
  28. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    A Scalable Communication-Centric SoC Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:343-348 [Conf]
  29. Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
    On Multiple Fault Coverage and Aliasing Probability Measures. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:314-321 [Conf]
  30. André Ivanov, Vinod K. Agarwal
    Testability Measures : What Do They Do for ATPG ? [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:129-139 [Conf]
  31. Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei
    Jitter Models and Measurement Methods for High-Speed Serial Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1295-1302 [Conf]
  32. D. Lambidonis, André Ivanov, Vinod K. Agarwal
    Fast Signature Computation for Linear Compactors. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:808-817 [Conf]
  33. Mohsen Nahvi, André Ivanov, Resve A. Saleh
    Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1176-1184 [Conf]
  34. Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
    Optimal conditions for Boolean and current detection of floating gate faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:477-486 [Conf]
  35. Sassan Tabatabaei, André Ivanov
    An Embedded Core for Sub-Picosecond Timing Measurements. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:129-137 [Conf]
  36. Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
    : Experiments on Aliasing in Signature Analysis Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:344-354 [Conf]
  37. Partha Pratim Pande, Cristian Grecu, André Ivanov
    High-Throughput Switch-Based Interconnect for Future SoCs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:304-310 [Conf]
  38. Baosheng Wang, Josh Yang, André Ivanov
    Reducing Test Time of Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:47-52 [Conf]
  39. Josh Yang, Baosheng Wang, André Ivanov
    Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:493-498 [Conf]
  40. Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov
    Sensing temperature in CMOS circuits for Thermal Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:179-184 [Conf]
  41. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    BIST for Network-on-Chip Interconnect Infrastructures. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:30-35 [Conf]
  42. André Ivanov
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:424-425 [Conf]
  43. Fidel Muradali, André Ivanov
    Do I Need this Tool for My Chips to Work? [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:471-472 [Conf]
  44. Mohsen Nahvi, André Ivanov
    An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:293-298 [Conf]
  45. Sassan Tabatabaei, André Ivanov
    A Current Integrator for BIST of Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:311-318 [Conf]
  46. Bapiraju Vinnakota, André Ivanov
    Biomedical ICs: What is Different about Testing those ICs? [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:329-332 [Conf]
  47. Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian
    SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:66-71 [Conf]
  48. Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian
    Reducing Embedded SRAM Test Time under Redundancy Constraints. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:237-242 [Conf]
  49. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
    An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:60-67 [Journal]
  50. Yuejian Wu, André Ivanov
    Reducing Hardware with Fuzzy Multiple Signature Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:68-74 [Journal]
  51. André Ivanov, Fabrizio Lombardi, Cecilia Metra
    Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:274-276 [Journal]
  52. André Ivanov, Giovanni De Micheli
    Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:399-403 [Journal]
  53. Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov
    Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:302-313 [Journal]
  54. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
    Design, Synthesis, and Test of Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:404-413 [Journal]
  55. Sassan Tabatabaei, André Ivanov
    Embedded Timing Analysis: A SoC Infrastructure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:24-36 [Journal]
  56. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:6-112 [Journal]
  57. Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov
    Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:149-160 [Journal]
  58. André Ivanov, Barry K. Tsuji, Yervant Zorian
    Programmable BIST Space Compactors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:12, pp:1393-1404 [Journal]
  59. Tiko Kameda, Slawomir Pilarski, André Ivanov
    Notes on Multiple Input Signature Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:2, pp:228-234 [Journal]
  60. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh
    Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:1025-1040 [Journal]
  61. Yuejian Wu, André Ivanov
    Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:6, pp:817-825 [Journal]
  62. Yervant Zorian, André Ivanov
    An Effective BIST Scheme for ROM's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:646-653 [Journal]
  63. André Ivanov, Vinod K. Agarwal
    Dynamic testability measures for ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:598-608 [Journal]
  64. André Ivanov, Vinod K. Agarwal
    An analysis of the probabilistic behavior of linear feedback signature registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1074-1088 [Journal]
  65. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
    On the detectability of CMOS floating gate transistor faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:116-128 [Journal]
  66. André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams
    Iterative algorithms for computing aliasing probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:260-265 [Journal]
  67. André Ivanov, Yervant Zorian
    Count-based BIST compaction schemes and aliasing probability computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:768-777 [Journal]
  68. D. Lambidonis, André Ivanov, Vinod K. Agarwal
    Fast signature computation for BIST linear compactors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1037-1044 [Journal]
  69. Mohsen Nahvi, André Ivanov
    Indirect test architecture for SoC testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1128-1142 [Journal]
  70. Slawomir Pilarski, Tiko Kameda, André Ivanov
    Sequential faults and aliasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1068-1074 [Journal]
  71. Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
    Using an asymmetric error model to study aliasing in signature analysis registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:16-25 [Journal]
  72. Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov
    Fast detection of data retention faults and other SRAM cell open defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:167-180 [Journal]
  73. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    Timing analysis of network on chip architectures for MP-SoC platforms. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:833-845 [Journal]
  74. Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh
    Essential Fault-Tolerance Metrics for NoC Infrastructures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:37-42 [Conf]
  75. Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu
    Towards Open Network-on-Chip Benchmarks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:205- [Conf]
  76. Baosheng Wang, Yuejian Wu, André Ivanov
    A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  77. Yvan Maidon, Thomas Zimmer, André Ivanov
    An Analog Circuit Fault Characterization Methodology. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:127-134 [Journal]
  78. Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei
    A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:621-630 [Journal]

  79. On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. [Citation Graph (, )][DBLP]


  80. Novel interconnect infrastructures for massive multicore chips - an overview. [Citation Graph (, )][DBLP]


Search in 0.005secs, Finished in 0.457secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002