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Minoru Watanabe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Minoru Watanabe, Fuminori Kobayashi
    A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:108-109 [Conf]
  2. Minoru Watanabe, Fuminori Kobayashi
    Testing Method for Optical Connections Using Gate Array Structure in ORGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:299-302 [Conf]
  3. Minoru Watanabe, Fuminori Kobayashi
    Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:311- [Conf]
  4. Minoru Watanabe, Fuminori Kobayashi
    Logic Synthesis and Place-and-Route Environment for ORGAs. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:237-238 [Conf]
  5. Minoru Watanabe, Fuminori Kobayashi
    Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:239-240 [Conf]
  6. Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
    Differential Reconfiguration Architecture suitable for a Holographic Memory. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:198-206 [Conf]
  7. Minoru Watanabe, Fuminori Kobayashi
    A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:261-269 [Conf]
  8. Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
    Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:287-288 [Conf]
  9. Minoru Watanabe, Fuminori Kobayashi
    A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:297-298 [Conf]
  10. Minoru Watanabe, Fuminori Kobayashi
    An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:188- [Conf]
  11. Minoru Watanabe, Fuminori Kobayashi
    An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  12. Minoru Watanabe, Fuminori Kobayashi
    Power consumption advantage of a dynamic optically reconfigurable gate array. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  13. Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
    An optically differential reconfigurable gate array with a holographic memory. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  14. Minoru Watanabe, Fuminori Kobayashi
    A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1214-1217 [Conf]
  15. Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
    Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:274-275 [Conf]
  16. Minoru Watanabe, Fuminori Kobayashi
    An Improved Dynamic Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:136-141 [Conf]
  17. Minoru Watanabe, Fuminori Kobayashi
    An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:735-0 [Conf]
  18. Minoru Watanabe, Fuminori Kobayashi
    A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  19. Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi
    A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  20. Minoru Watanabe, Fuminori Kobayashi
    Holographic memory reconfigurable VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:401-404 [Conf]
  21. Minoru Watanabe, Fuminori Kobayashi
    A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:268-273 [Conf]

  22. Dynamic holographic reconfiguration on a four-context ODRGA. [Citation Graph (, )][DBLP]


  23. A 16-context Optically Reconfigurable Gate Array. [Citation Graph (, )][DBLP]


  24. An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. [Citation Graph (, )][DBLP]


  25. 272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. [Citation Graph (, )][DBLP]


  26. A Multi-Context Programmable Optically Reconfigurable Gate Array. [Citation Graph (, )][DBLP]


  27. MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. [Citation Graph (, )][DBLP]


  28. A 770ns Holographic Reconfiguration of a Four-Context DORGA. [Citation Graph (, )][DBLP]


  29. Alignment compensation method for an optically reconfigurable gate array. [Citation Graph (, )][DBLP]


  30. Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. [Citation Graph (, )][DBLP]


  31. Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory. [Citation Graph (, )][DBLP]


  32. Mems optically reconfigurable gate array. [Citation Graph (, )][DBLP]


  33. A nine-context programmable optically reconfigurable gate array with semiconductor lasers. [Citation Graph (, )][DBLP]


  34. Defect tolerance of holographic configurations in ORGAs. [Citation Graph (, )][DBLP]


  35. A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. [Citation Graph (, )][DBLP]


  36. A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. [Citation Graph (, )][DBLP]


  37. Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. [Citation Graph (, )][DBLP]


  38. An Acceleration and Optimization Method for Optical Reconfiguration. [Citation Graph (, )][DBLP]


  39. An Optical Reconfiguration System with Four Contexts. [Citation Graph (, )][DBLP]


  40. Fast Optical Reconfiguration of a Nine-Context DORGA. [Citation Graph (, )][DBLP]


  41. MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. [Citation Graph (, )][DBLP]


  42. Analysis of retention time under multi-configuration on a DORGA. [Citation Graph (, )][DBLP]


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