The SCEAS System
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## Search the dblp DataBase
Hideki Asai:
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## Publications of Author- Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai
**Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:832-837 [Conf] - Yuichi Tanji, Hideki Asai
**Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:810-813 [Conf] - Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
**Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1327-1333 [Conf] - Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
**Large scale RLC circuit analysis using RLCG-MNA formulation.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:45-46 [Conf] - Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya
**Design Method of Limit Cycle Generator by Hysteresis Neural Networks.**[Citation Graph (0, 0)][DBLP] IJCNN (3), 2000, pp:500-505 [Conf] - Masahiro Yoshida, Hideki Asai, Takeshi Kamio
**Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform.**[Citation Graph (0, 0)][DBLP] IJCNN (3), 2000, pp:315-319 [Conf] - Vijaya Gopal Bandi, Hideki Asai
**Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:419-422 [Conf] - Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai
**Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:411-414 [Conf] - Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai
**Convergence of Hopfield Neural Network for Orthogonal Transformation.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:493-496 [Conf] - Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
**Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2005, pp:4903-4906 [Conf] - Hiroshi Ninomiya, Hideki Asai
**Orthogonalized Steepest Descent Method for Solving Nonlinear Equations.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:740-743 [Conf] - Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai
**Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:9-12 [Conf] - Takeshi Senoo, Hiroaki Makino, Hideki Asai
**Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:5-8 [Conf] - Takayuki Watanabe, Hideki Asai
**Analysis of PCB interconnects using electromagnetic reduction technique.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2003, pp:498-501 [Conf] - Takayuki Watanabe, Hideki Asai
**Modeling of power distribution networks with signal lines for SPICE simulators.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 2005, pp:5774-5777 [Conf] - Masaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
**High-speed interconnect simulation using MIMO type of adaptive least square method.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2001, pp:327-330 [Conf] - Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
**Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:393-400 [Conf] - Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai
**New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data.**[Citation Graph (0, 0)][DBLP] IEICE Transactions, 2005, v:88, n:2, pp:524-532 [Journal] - Shinsuke Manabe, Hideki Asai
**A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation.**[Citation Graph (0, 0)][DBLP] Neural Processing Letters, 2001, v:13, n:3, pp:267-275 [Journal] - Yuya Nakazono, Hideki Asai
**Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1489-1492 [Conf] - Y. Tanji, H. Asai, M. Oda, Y. Nishio, A. Ushida
**Fast timing analysis of plane circuits via two-layer CNN-based modeling.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai
**Three dimensional module packing by simulated annealing.**[Citation Graph (0, 0)][DBLP] Congress on Evolutionary Computation, 2005, pp:1069-1074 [Conf] **Generating stable and sparse reluctance/inductance matrix under insufficient conditions.**[Citation Graph (, )][DBLP]**Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation.**[Citation Graph (, )][DBLP]
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