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Wolfgang Kunz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Exploiting state encoding for invariant generation in induction-based property checking. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:424-429 [Conf]
  2. Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan
    Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:414-419 [Conf]
  3. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Normalization at the arithmetic bit level. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:457-462 [Conf]
  4. Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken
    Improving Placement under the Constant Delay Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:677-682 [Conf]
  5. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Using RTL Statespace Information and State Encoding for Induction Based Property Checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11156-11157 [Conf]
  6. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Arithmetic Reasoning in DPLL-Based SAT Solving. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:30-35 [Conf]
  7. Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz
    Accelerating Boolean Implications with FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:532-537 [Conf]
  8. Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz
    Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:303-307 [Conf]
  9. Armin Biere, Wolfgang Kunz
    SAT and ATPG: Boolean engines for formal hardware verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:782-785 [Conf]
  10. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: logic optimization with testability-new transformations using recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:318-325 [Conf]
  11. Wolfgang Kunz
    HANNIBAL: an efficient tool for logic verification based on recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:538-543 [Conf]
  12. Wolfgang Kunz, Premachandran R. Menon
    Multi-level logic optimization by implication analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:6-13 [Conf]
  13. Ingmar Neumann, Wolfgang Kunz
    Placement Driven Retiming with a Coupled Edge Timing Model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:95-102 [Conf]
  14. Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz
    Cell replication and redundancy elimination during placement for cycle time optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:25-30 [Conf]
  15. Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
    Transition-by-transition FSM traversal for reachability analysis in bounded model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1068-1075 [Conf]
  16. Dominik Stoffel, Wolfgang Kunz
    Verification of Integer Multipliers on the Arithmetic Bit Level. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:183-189 [Conf]
  17. Dominik Stoffel, Wolfgang Kunz
    Record & play: a structural fixed point iteration for sequential circuit verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:394-399 [Conf]
  18. Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
    Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:350-353 [Conf]
  19. Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz
    Cycle time optimization by timing driven placement with simultaneous netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:359-362 [Conf]
  20. Ingmar Neumann, Wolfgang Kunz
    Tight coupling of timing-driven placement and retiming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:351-354 [Conf]
  21. Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
    Gate-level synthesis for low-power using new transformations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:297-300 [Conf]
  22. Kolja Sulimma, Wolfgang Kunz
    An exact algorithm for solving difficult detailed routing problems. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:198-203 [Conf]
  23. Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
    Accelerating Retiming Under the Coupled-Edge Timing Model. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:135-140 [Conf]
  24. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:151-158 [Conf]
  25. Wolfgang Kunz, Dhiraj K. Pradhan
    Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:816-825 [Conf]
  26. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: Logic Optimization with Testability. New transformations for logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:386-399 [Journal]
  27. Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon
    Logic optimization and equivalence checking by implication analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:266-281 [Journal]
  28. Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
    A novel framework for logic verification in a synthesis environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:20-32 [Journal]
  29. Wolfgang Kunz, Dhiraj K. Pradhan
    Accelerated dynamic learning for test pattern generation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:684-694 [Journal]
  30. Wolfgang Kunz, Dhiraj K. Pradhan
    Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1143-1158 [Journal]
  31. Ingmar Neumann, Wolfgang Kunz
    Layout driven retiming using the coupled edge timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:825-835 [Journal]
  32. Dominik Stoffel, Wolfgang Kunz
    Equivalence checking of arithmetic circuits on the arithmetic bit level. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:586-597 [Journal]
  33. Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz
    Structural FSM traversal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:598-619 [Journal]

  34. Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. [Citation Graph (, )][DBLP]


  35. An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths. [Citation Graph (, )][DBLP]


  36. Analyzing k-step induction to compute invariants for SAT-based property checking. [Citation Graph (, )][DBLP]


  37. Modeling of Custom-Designed Arithmetic Components for ABL Normalization. [Citation Graph (, )][DBLP]


  38. Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. [Citation Graph (, )][DBLP]


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