The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Kaijie Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu
    Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1192-1195 [Conf]
  2. Nikhil Joshi, Kaijie Wu, Ramesh Karri
    Concurrent Error Detection Schemes for Involution Ciphers. [Citation Graph (0, 0)][DBLP]
    CHES, 2004, pp:400-412 [Conf]
  3. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:579-585 [Conf]
  4. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure scan: a design-for-test architecture for crypto chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:135-140 [Conf]
  5. Kaijie Wu, Ramesh Karri
    Exploiting Idle Cycles for Algorithm Level Re-Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:842-846 [Conf]
  6. Kyosun Kim, Kaijie Wu, Ramesh Karri
    owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1214-1219 [Conf]
  7. Kaijie Wu, Ramesh Karri
    Idle Cycles Based Concurrent Error Detection of RC6 Encryption. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:200-205 [Conf]
  8. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:427-435 [Conf]
  9. Kaijie Wu, Ramesh Karri
    Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:537-0 [Conf]
  10. Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang
    Online task-scheduling for fault-tolerant low-energy real-time systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:522-527 [Conf]
  11. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:971-978 [Conf]
  12. Kaijie Wu, Ramesh Karri
    Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:221-229 [Conf]
  13. Kaijie Wu, Ramesh Karri
    Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:902-911 [Conf]
  14. Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel
    Low Cost Concurrent Error Detection for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1242-1248 [Conf]
  15. Bo Yang, Kaijie Wu, Ramesh Karri
    Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:339-344 [Conf]
  16. Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri
    Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:10, pp:1230-1239 [Journal]
  17. Han Liang, Piyush Mishra, Kaijie Wu
    Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:243-252 [Journal]
  18. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1509-1517 [Journal]
  19. Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri
    Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1163-1169 [Journal]
  20. Kaijie Wu, Ramesh Karri
    Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1077-1087 [Journal]
  21. Kaijie Wu, Ramesh Karri
    Fault secure datapath synthesis using hybrid time and hardware redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1476-1485 [Journal]
  22. Kaijie Wu, Ramesh Karri
    Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:413-422 [Journal]
  23. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure Scan: A Design-for-Test Architecture for Crypto Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2287-2293 [Journal]
  24. Kaijie Wu, Ramesh Karri
    Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:501-511 [Journal]
  25. Ramesh Karri, Kaijie Wu
    Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:864-875 [Journal]
  26. Kaijie Wu, Piyush Mishra, Ramesh Karri
    Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:31-39 [Journal]

  27. Scheduling for energy efficiency and fault tolerance in hard real-time systems. [Citation Graph (, )][DBLP]


  28. An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level. [Citation Graph (, )][DBLP]


  29. Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. [Citation Graph (, )][DBLP]


Search in 0.014secs, Finished in 0.016secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002