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André DeHon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael G. Wrighton, André DeHon
    SAT-based optimal hypergraph partitioning with replication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:789-795 [Conf]
  2. André DeHon, John Wawrzynek
    Reconfigurable Computing: What, Why, and Implications for Design Automation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:610-615 [Conf]
  3. Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
    Object Oriented Circuit-Generators in Java. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:158-166 [Conf]
  4. André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton
    Design Patterns for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:13-23 [Conf]
  5. André DeHon, Randy Huang, John Wawrzynek
    Hardware-Assisted Fast Routing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:205-0 [Conf]
  6. Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon
    GraphStep: A System Architecture for Sparse-Graph Algorithms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:143-151 [Conf]
  7. Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon
    Packet Switched vs. Time Multiplexed FPGA Overlay Networks. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:205-216 [Conf]
  8. André DeHon
    Design of programmable interconnect for sublithographic programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:127-137 [Conf]
  9. André DeHon
    Entropy, Counting, and Programmable Interconnect. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:73-79 [Conf]
  10. André DeHon
    DPGA Utilization and Application. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:115-121 [Conf]
  11. André DeHon
    Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:69-78 [Conf]
  12. André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
    What is the right model for programming and using modern FPGAs? [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:119- [Conf]
  13. André DeHon, Michael J. Wilson
    Nanowire-based sublithographic programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:123-132 [Conf]
  14. Michael DeLorimier, André DeHon
    Floating-point sparse matrix-vector multiply for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:75-85 [Conf]
  15. Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek
    Fast Module Mapping and Placement for Datapaths in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:123-132 [Conf]
  16. Randy Huang, John Wawrzynek, André DeHon
    Stochastic, spatial routing for hypergraphs, trees, and meshes. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:78-87 [Conf]
  17. Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
    Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:196-205 [Conf]
  18. Raphael Rubin, André DeHon
    Design of FPGA interconnect for multilevel metalization. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:154-163 [Conf]
  19. Michael G. Wrighton, André DeHon
    Hardware-assisted simulated annealing with application for fast FPGA placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:33-42 [Conf]
  20. William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon
    HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:125-134 [Conf]
  21. Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
    Stream Computations Organized for Reconfigurable Execution (SCORE). [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:605-614 [Conf]
  22. Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon
    Pipelining Saturated Accumulation. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:19-26 [Conf]
  23. André DeHon
    Directions in General-Purpose Computing Architectures. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:717-718 [Conf]
  24. Michael Butts, André DeHon, Seth Copen Goldstein
    Molecular electronics: devices, systems and tools for gigagate, gigabit chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:433-440 [Conf]
  25. André DeHon, Konstantin Likharev
    Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:375-382 [Conf]
  26. Frederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.
    METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:266-277 [Conf]
  27. Rajiv V. Joshi, Kaustav Banerjee, André DeHon
    Tutorial 1: Emerging Technologies for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:4- [Conf]
  28. André DeHon
    In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:350-359 [Conf]
  29. Ian Eslick, André DeHon, Thomas F. Knight Jr.
    Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1994, pp:215-225 [Conf]
  30. André DeHon
    Rent's rule based switching requirements. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:197-204 [Conf]
  31. André DeHon
    Compact, multilayer layout for butterfly fat-tree. [Citation Graph (0, 0)][DBLP]
    SPAA, 2000, pp:206-215 [Conf]
  32. André DeHon
    Very Large Scale Spatial Computing. [Citation Graph (0, 0)][DBLP]
    UMC, 2002, pp:27-36 [Conf]
  33. André DeHon
    The Density Advantage of Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:41-49 [Journal]
  34. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
  35. André DeHon, Helia Naeimi
    Seven Strategies for Tolerating Highly Defective Fabrication. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:306-315 [Journal]
  36. André DeHon
    Nanowire-based programmable architectures. [Citation Graph (0, 0)][DBLP]
    JETC, 2005, v:1, n:2, pp:109-162 [Journal]
  37. John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu
    Radial addressing of nanowires. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:2, pp:129-154 [Journal]
  38. André DeHon, Craig S. Lent, Fabrizio Lombardi
    Introduction to the Special Section on Nano Systems and Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:145-146 [Journal]
  39. André DeHon
    Unifying mesh- and tree-based programmable interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1051-1065 [Journal]
  40. André DeHon, Raphael Rubin
    Design of FPGA interconnect for multilevel metallization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1038-1050 [Journal]
  41. André DeHon, Randy Huang, John Wawrzynek
    Stochastic spatial routing for reconfigurable networks. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:301-318 [Journal]
  42. André DeHon, Yury Markovskiy, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
    Stream computations organized for reconfigurable execution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:334-354 [Journal]
  43. Nachiket Kapre, André DeHon
    Optimistic Parallelization of Floating-Point Accumulation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:205-216 [Conf]

  44. 06361 Executive Report -- Computing Media Languages for Space-Oriented Computation. [Citation Graph (, )][DBLP]


  45. 06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation. [Citation Graph (, )][DBLP]


  46. Vision for cross-layer optimization to address the dual challenges of energy and reliability. [Citation Graph (, )][DBLP]


  47. Fault Secure Encoder and Decoder for Memory Applications. [Citation Graph (, )][DBLP]


  48. Accelerating SPICE Model-Evaluation using FPGAs. [Citation Graph (, )][DBLP]


  49. Choose-your-own-adventure routing: lightweight load-time defect avoidance. [Citation Graph (, )][DBLP]


  50. CMOS vs Nano: comrades or rivals? [Citation Graph (, )][DBLP]


  51. Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. [Citation Graph (, )][DBLP]


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