Search the dblp DataBase

Publications of Author

1. Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang
   Delay variation tolerance for domino circuits. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:354-359 [Conf]
   
2. Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu
   Re-synthesis for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:814-819 [Conf]
   
3. 
   Soft error rate reduction using redundancy addition and removal. [Citation Graph (, )][DBLP]
   
   
4. 
   Joint logic restructuring and pin reordering against NBTI-induced performance degradation. [Citation Graph (, )][DBLP]
   
   
5. 
   Clock skew scheduling for soft-error-tolerant sequential circuits. [Citation Graph (, )][DBLP]
   
   
6. 
   Process variability-aware transient fault modeling and analysis. [Citation Graph (, )][DBLP]
   
   
7. 
   Power-aware soft error hardening via selective voltage scaling. [Citation Graph (, )][DBLP]