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Cheng-Tao Hsieh:
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- Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang
Delay variation tolerance for domino circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:354-359 [Conf]
- Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu
Re-synthesis for delay variation tolerance. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:814-819 [Conf]
- Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang
A vectorless estimation of maximum instantaneous current for sequential circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:537-540 [Conf]
- Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. [Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:602-606 [Conf]
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. [Citation Graph (, )][DBLP]
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