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Publications of Author

1. Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
   Redundant-via enhanced maze routing for yield improvement. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1148-1151 [Conf]
   
2. Li-Da Huang, Martin D. F. Wong
   Optical proximity correction (OPC): friendly maze routing. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:186-191 [Conf]
   
3. Li-Da Huang, Hung-Ming Chen, D. F. Wong
   Global Wire Bus Configuration with Minimum Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10050-10055 [Conf]
   
4. Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
   Maze Routing with Buffer Insertion under Transition Time Constraints. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:702-707 [Conf]
   
5. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
   A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:470-477 [Conf]
   
6. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
   I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:562-567 [Conf]
   
7. Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
   Explicit gate delay model for timing evaluation. [Citation Graph (0, 0)][DBLP]
   ISPD, 2003, pp:32-38 [Conf]
   
8. Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
   OPC-Friendly Bus Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:847-852 [Conf]
   
9. Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
   Simultaneous power supply planning and noise avoidance in floorplan design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:578-587 [Journal]
   
10. Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
    Maze routing with buffer insertion under transition time constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:91-95 [Journal]
    
11. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
    
12. 
    Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. [Citation Graph (, )][DBLP]
    
    
13. 
    A stochastic-based efficient critical area extractor on OpenAccess platform. [Citation Graph (, )][DBLP]