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Hiroaki Yamaoka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2001, pp:3-4 [Conf] - Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2002, pp:166-171 [Conf] - H. Yoshida, H. Yamaoka, M. Ikeda, K. Asada
Logic synthesis for PLA with 2-input logic elements. [Citation Graph (0, 0)][DBLP]
ISCAS (3), 2002, pp:373-376 [Conf] - Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2002, pp:166-171 [Conf]
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