The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Saburo Muroga: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yahiko Kambayashi, Saburo Muroga
    Properties of Wired Logic. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:6, pp:550-563 [Journal]
  2. Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney
    The Transduction Method-Design of Logic Networks Based on Permissible Functions. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:10, pp:1404-1424 [Journal]
  3. Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
    Optimization methods for lookup-table-based FPGAs using transduction method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Kuang-Chien Chen, Saburo Muroga
    Timing Optimization for Multi-Level Combinational Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:339-344 [Conf]
  5. Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
    A Resynthesis Approach for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:458-463 [Conf]
  6. Johnson Chan Limqueco, Saburo Muroga
    Logic Optimization of MOS Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:464-469 [Conf]
  7. Calvin C. Elgot, Saburo Muroga
    Two problems on threshold functions [Citation Graph (0, 0)][DBLP]
    FOCS, 1961, pp:166- [Conf]
  8. Saburo Muroga
    Functional forms of majority functions and a necessary and sufficient condition for their realizability [Citation Graph (0, 0)][DBLP]
    FOCS, 1961, pp:39-46 [Conf]
  9. Saburo Muroga
    Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight [Citation Graph (0, 0)][DBLP]
    FOCS, 1962, pp:169-184 [Conf]
  10. Saburo Muroga
    The principle of majority decision logical elements and the complexity of their circuits. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1959, pp:400-406 [Conf]
  11. Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga
    A Shared Memory Parallel Algorithm for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:317-322 [Conf]
  12. Saburo Muroga
    Computer-Aided Logic Synthesis for VLSI Chips. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 1991, v:32, n:, pp:1-103 [Journal]
  13. Jay Niel Culliney, Ming Huei Young, T. Nakagawa, Saburo Muroga
    Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:1, pp:76-85 [Journal]
  14. Robert Brian Cutler, Saburo Muroga
    Comments on ``Computing Irredundant Normal Forms from Abbreviated Presence Functions''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:11, pp:874-875 [Journal]
  15. Robert Brian Cutler, Saburo Muroga
    Comments on ``Generalization of Consensus Theory and Application to the Minimization of Boolean Functions''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:7, pp:542-543 [Journal]
  16. Robert Brian Cutler, Saburo Muroga
    Derivation of Minimal Sums for Completely Specified Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:277-292 [Journal]
  17. Sung Je Hong, Saburo Muroga
    Absolute Minimization of Completely Specified Switching Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:53-65 [Journal]
  18. Hung Chi Lai, Saburo Muroga
    Minimum Parallel Binary Adders with NOR (NAND) Gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:648-659 [Journal]
  19. Hung Chi Lai, Saburo Muroga
    Logic Networks of Carry-Save Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:9, pp:870-882 [Journal]
  20. Hung Chi Lai, Saburo Muroga
    Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:2, pp:157-166 [Journal]
  21. Saburo Muroga, Hung Chi Lai
    Minimization of Logic Networks Under a Generalized Cost Function. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:9, pp:893-907 [Journal]
  22. Akito Sakurai, Saburo Muroga
    Parallel Binary Adders with a Minimum Number of Connections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:10, pp:969-976 [Journal]
  23. Ming Huei Young, Saburo Muroga
    Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:6, pp:523-541 [Journal]
  24. Hung Chi Lai, Saburo Muroga
    Design of MOS networks in single-rail input logic for incompletely specified functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:339-345 [Journal]

Search in 0.027secs, Finished in 0.029secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002