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Xiaodong Yang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
    A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:463-468 [Conf]
  2. Song Lu, BaoHua Fan, Yong Dou, Xiaodong Yang
    Clustering Multicast on Hypercube Network. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:61-70 [Conf]
  3. Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher
    Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:222-228 [Conf]
  4. Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
    RLC interconnect delay estimation via moments of amplitude and phase response. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:208-213 [Conf]
  5. Xiaodong Yang, Houqiang Li, Xiaobo Zhou, Stephen T. C. Wong
    Identification of Cell-Cycle Phases Using Neural Network and Steerable Filter Features. [Citation Graph (0, 0)][DBLP]
    ISNN (2), 2006, pp:702-709 [Conf]
  6. Shaogang Wang, Dan Wu, Xiaodong Yang, Zhengbin Pang
    Exploring Data Reusing of Failed Transaction. [Citation Graph (0, 0)][DBLP]
    APPT, 2007, pp:141-150 [Conf]
  7. Xiaodong Yang, Shengmei Mou, Yong Dou
    FPGA-Accelerated Molecular Dynamics Simulations: An Overview. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:293-301 [Conf]

  8. A Clustering Model for Multicast on Hypercube Network. [Citation Graph (, )][DBLP]

  9. Software Assisted Transact Cache to Support Efficient Unbounded Transactional Memory. [Citation Graph (, )][DBLP]

  10. A Multicast Path Algorithm on Hypercube Interconnection Networks. [Citation Graph (, )][DBLP]

  11. Computer Vision-Based Door Detection for Accessibility of Unfamiliar Environments to Blind Persons. [Citation Graph (, )][DBLP]

  12. DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System. [Citation Graph (, )][DBLP]

  13. Design of a High-speed FPGA-based 32-bit Floating-point FFT Processor. [Citation Graph (, )][DBLP]

  14. Research on the RAW Dependency in Floating-point FFT Processors. [Citation Graph (, )][DBLP]

  15. Explicit Model Checking Based on Integer Pointer and Fibonacci Hash. [Citation Graph (, )][DBLP]

  16. Efficient Verification of Parameterized Cache Coherence Protocols. [Citation Graph (, )][DBLP]

  17. Lowering the Overhead of Hybrid Transactional Memory with Transact Cache. [Citation Graph (, )][DBLP]

  18. A survey of handover algorithms in DVB-H. [Citation Graph (, )][DBLP]

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