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Marek A. Perkowski :
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Guowu Yang , Xiaoyu Song , William N. N. Hung , Marek A. Perkowski Fast synthesis of exact minimal reversible circuits using group theory. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1002-1005 [Conf ] Rolf Drechsler , Andisheh Sarabi , Michael Theobald , Bernd Becker , Marek A. Perkowski Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:415-419 [Conf ] William N. N. Hung , Xiaoyu Song , Guowu Yang , Jin Yang , Marek A. Perkowski Quantum logic synthesis by symbolic reachability analysis. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:838-841 [Conf ] Martin Helliwell , Marek A. Perkowski A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:427-432 [Conf ] Alan Mishchenko , Bernd Steinbach , Marek A. Perkowski An Algorithm for Bi-Decomposition of Logic Functions. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:103-108 [Conf ] Marek A. Perkowski , Rahul Malvi , Stan Grygiel , Michael Burns , Alan Mishchenko Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:225-230 [Conf ] Andisheh Sarabi , Marek A. Perkowski Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:30-35 [Conf ] Andisheh Sarabi , Ning Song , Malgorzata Chrzanowska-Jeske , Marek A. Perkowski A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:321-326 [Conf ] Guowu Yang , William N. N. Hung , Xiaoyu Song , Marek A. Perkowski Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:434-435 [Conf ] Marek A. Perkowski , Malgorzata Chrzanowska-Jeske , Alan Mishchenko , Xiaoyu Song , Anas Al-Rabadi , Bart Massey , Pawel Kerntopf , Andrzej Buller , Lech Józwiak , Alan J. Coppola Regular Realization of Symmetric Functions Using Reversible Logic. [Citation Graph (0, 0)][DBLP ] DSD, 2001, pp:245-253 [Conf ] Marek A. Perkowski , Pawel Kerntopf Fundamentals of Reversible Logic and Computing. [Citation Graph (0, 0)][DBLP ] DSD, 2001, pp:244-0 [Conf ] Martin Lukac , Marek A. Perkowski Evolving Quantum Circuits Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Evolvable Hardware, 2002, pp:177-185 [Conf ] Andrzej Buller , Marek A. Perkowski Evolved Reversible Cascades Realized on the CAM-Brain Machine. [Citation Graph (0, 0)][DBLP ] Evolvable Hardware, 2003, pp:256-264 [Conf ] Chong H. Lee , Marek A. Perkowski , Douglas V. Hall , David S. Jun Self-Repairable EPLDs: Design, Self-Repair, and Evaluation Methodology. [Citation Graph (0, 0)][DBLP ] Evolvable Hardware, 2000, pp:183-194 [Conf ] Marek A. Perkowski , Alan Mishchenko , Anatoli N. Chebotarev Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. [Citation Graph (0, 0)][DBLP ] Evolvable Hardware, 1999, pp:129-138 [Conf ] Michael Burns , Marek A. Perkowski , Lech Józwiak An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10016-10023 [Conf ] Sanof Mohamed , Marek A. Perkowski , Lech Józwiak Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1997, pp:31-0 [Conf ] Torrey Lewis , Marek A. Perkowski , Lech Józwiak Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1999, pp:1326-1334 [Conf ] Loc Bao Nguen , Marek A. Perkowski , Lech Józwiak Design of Self-Synchronized Component FSMs for Self-Timed Systems. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10253-10260 [Conf ] Ning Song , Marek A. Perkowski A New Approach to And/Or/Exor Factorization for Regular Array. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10269-0 [Conf ] Li-Fei Wu , Marek A. Perkowski Minimization of Permuted Reed-Muller Trees for Cellular Logic. [Citation Graph (0, 0)][DBLP ] FPL, 1992, pp:78-87 [Conf ] Marek A. Perkowski , Laszlo Csanky , Andisheh Sarabi , Ingo Schäfer Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:33-36 [Conf ] Alan J. Coppola , Marek A. Perkowski , Robert Anderson , Jeffrey S. Freedman , Edmund Pierzchala Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs. [Citation Graph (0, 0)][DBLP ] Synthesis for Control Dominated Circuits, 1992, pp:33-46 [Conf ] Edmund Pierzchala , Rolf Schaumann , Paul Van Halen , Stanislaw Szczepanski , Marek A. Perkowski Highly Linear VHF Current-Mode Miller Integrator with 900 dB DC Gain. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:1852-1855 [Conf ] Anas Al-Rabadi , Marek A. Perkowski Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity. [Citation Graph (0, 0)][DBLP ] ISMVL, 2001, pp:159-166 [Conf ] Bogdan J. Falkowski , Marek A. Perkowski Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1990, pp:75-82 [Conf ] Craig M. Files , Rolf Drechsler , Marek A. Perkowski Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP ] ISMVL, 1997, pp:27-0 [Conf ] Craig M. Files , Marek A. Perkowski An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition. [Citation Graph (0, 0)][DBLP ] ISMVL, 1998, pp:167-172 [Conf ] Craig M. Files , Marek A. Perkowski Multi-Valued Functional Decomposition as a Machine Learning Method. [Citation Graph (0, 0)][DBLP ] ISMVL, 1998, pp:173-0 [Conf ] Stan Grygiel , Marek A. Perkowski , Malgorzata Marek-Sadowska , Tadeusz Luba , Lech Józwiak Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. [Citation Graph (0, 0)][DBLP ] ISMVL, 1997, pp:287-292 [Conf ] Qinhua Hong , Benchu Fei , Haomin Wu , Marek A. Perkowski , Nan Zhuang Fast Synthesis for Ternary Reed-Muller Expansion. [Citation Graph (0, 0)][DBLP ] ISMVL, 1993, pp:14-16 [Conf ] Ugur Kalay , Marek A. Perkowski , Douglas V. Hall Highly Testable Boolean Ring Logic Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1999, pp:268-274 [Conf ] Pawel Kerntopf , Marek A. Perkowski , Mozammel H. A. Khan On Universality of General Reversible Multiple-Valued Logic Gates. [Citation Graph (0, 0)][DBLP ] ISMVL, 2004, pp:68-73 [Conf ] Mozammel H. A. Khan , Marek A. Perkowski , Pawel Kerntopf Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades. [Citation Graph (0, 0)][DBLP ] ISMVL, 2003, pp:146-153 [Conf ] Mozammel H. A. Khan , Marek A. Perkowski , Mujibur R. Khan Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization. [Citation Graph (0, 0)][DBLP ] ISMVL, 2004, pp:58-67 [Conf ] Lun Li , Mitchell A. Thornton , Marek A. Perkowski A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. [Citation Graph (0, 0)][DBLP ] ISMVL, 2006, pp:33- [Conf ] Marek A. Perkowski A Universal Logic Machine. [Citation Graph (0, 0)][DBLP ] ISMVL, 1992, pp:262-271 [Conf ] Marek A. Perkowski The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications. [Citation Graph (0, 0)][DBLP ] ISMVL, 1992, pp:442-450 [Conf ] Marek A. Perkowski , Jacob Biamonte , Martin Lukac Test Generation and Fault Localization for Quantum Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 2005, pp:62-68 [Conf ] Marek A. Perkowski , Malgorzata Chrzanowska-Jeske Multiple-Valued-Input TANT Networks. [Citation Graph (0, 0)][DBLP ] ISMVL, 1994, pp:334-341 [Conf ] Marek A. Perkowski , Malgorzata Marek-Sadowska , Lech Józwiak , Tadeusz Luba , Stan Grygiel , Miroslawa Nowicka , Rahul Malvi , Zhi Wang , Jin S. Zhang Decomposition of Multiple-Valued Relations . [Citation Graph (0, 0)][DBLP ] ISMVL, 1997, pp:13-18 [Conf ] Marek A. Perkowski , Tsutomu Sasao , Jong-Hwan Kim , Martin Lukac , Jeff Allen , Stefan Gebauer Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem. [Citation Graph (0, 0)][DBLP ] ISMVL, 2005, pp:236-248 [Conf ] Edmund Pierzchala , Marek A. Perkowski , Stan Grygiel A Filed Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications. [Citation Graph (0, 0)][DBLP ] ISMVL, 1994, pp:148-155 [Conf ] Ingo Schäfer , Marek A. Perkowski Multiple-Valued Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP ] ISMVL, 1991, pp:40-48 [Conf ] Haomin Wu , Nan Zhuang , Marek A. Perkowski Novel CMOS Scan Design for VLSI Testability. [Citation Graph (0, 0)][DBLP ] ISMVL, 1993, pp:82-86 [Conf ] Ning Song , Marek A. Perkowski EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP ] ISMVL, 1993, pp:132-137 [Conf ] Ning Song , Marek A. Perkowski Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays. [Citation Graph (0, 0)][DBLP ] ISMVL, 1998, pp:32-37 [Conf ] Bernd Steinbach , Marek A. Perkowski , Christian Lang Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications. [Citation Graph (0, 0)][DBLP ] ISMVL, 1999, pp:50-58 [Conf ] Guowu Yang , Xiaoyu Song , William N. N. Hung , Marek A. Perkowski Bi-Direction Synthesis for Reversible Circuits. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2005, pp:14-19 [Conf ] Andrei B. Khlopotine , Marek A. Perkowski , Pawel Kerntopf Reversible Logic Synthesis by Iterative Compositions. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:261-266 [Conf ] Alan Mishchenko , Marek A. Perkowski Logic Synthesis of Reversible Wave Cascades. [Citation Graph (0, 0)][DBLP ] IWLS, 2002, pp:197-202 [Conf ] Guowu Yang , Xiaoyu Song , William N. N. Hung , Fei Xie , Marek A. Perkowski Group Theory Based Synthesis of Binary Reversible Circuits. [Citation Graph (0, 0)][DBLP ] TAMC, 2006, pp:365-374 [Conf ] Guowu Yang , Fei Xie , Xiaoyu Song , Marek A. Perkowski Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits. [Citation Graph (0, 0)][DBLP ] CIAA, 2006, pp:279-280 [Conf ] Martin Lukac , Marek A. Perkowski , Hilton Goi , Mikhail Pivtoraiko , Chung Hyo Yu , Kyusik Chung , Hyunkoo Jeech , Byung-Guk Kim , Yong Duk Kim Evolutionary Approach to Quantum and Reversible Circuits Synthesis. [Citation Graph (0, 0)][DBLP ] Artif. Intell. Rev., 2003, v:20, n:3-4, pp:361-417 [Journal ] Marek A. Perkowski , David Foote , Qihong Chen , Anas Al-Rabadi , Lech Józwiak Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2002, v:22, n:3, pp:41-51 [Journal ] Marek A. Perkowski , David Foote , Qihong Chen , Anas Al-Rabadi , Lech Józwiak Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2002, v:22, n:3, pp:52-61 [Journal ] Xiaoyu Song , Guowu Yang , Marek A. Perkowski , Yuke Wang Algebraic Characterization of Reversible Logic Gates. [Citation Graph (0, 0)][DBLP ] Theory Comput. Syst., 2006, v:39, n:2, pp:311-319 [Journal ] Ugur Kalay , Douglas V. Hall , Marek A. Perkowski A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2000, v:49, n:3, pp:267-276 [Journal ] Haomin Wu , Marek A. Perkowski , Xiaoqiang Zheng , Nan Zhuang Generalized Partially-Mixed-Polarity Reed-Muller Expansionand Its Fast Computation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:9, pp:1084-1088 [Journal ] Bogdan J. Falkowski , Ingo Schäfer , Marek A. Perkowski Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1207-1226 [Journal ] Craig M. Files , Marek A. Perkowski New multivalued functional decomposition algorithms based on MDDs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1081-1086 [Journal ] William N. N. Hung , Xiaoyu Song , Guowu Yang , Jin Yang , Marek A. Perkowski Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1652-1663 [Journal ] Ingo Schäfer , Marek A. Perkowski Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1655-1664 [Journal ] Ning Song , Marek A. Perkowski Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:385-395 [Journal ] Guowu Yang , William N. N. Hung , Xiaoyu Song , Marek A. Perkowski Majority-based reversible logic gates. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 2005, v:334, n:1-3, pp:259-274 [Journal ] Faisal Shah Khan , Marek A. Perkowski Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 2006, v:367, n:3, pp:336-346 [Journal ] Guowu Yang , William N. N. Hung , Xiaoyu Song , Marek A. Perkowski Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Mozammel H. A. Khan , Marek A. Perkowski Quantum ternary parallel adder/subtractor with partially-look-ahead carry. [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2007, v:53, n:7, pp:453-464 [Journal ] Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping. [Citation Graph (, )][DBLP ] GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. [Citation Graph (, )][DBLP ] Quantum Robots for Teenagers. [Citation Graph (, )][DBLP ] Quantum Mechanical Model of Emotional Robot Behaviors. [Citation Graph (, )][DBLP ] Projective Measurement-Based Logic Synthesis of Quantum Circuits. [Citation Graph (, )][DBLP ] Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID). [Citation Graph (, )][DBLP ] Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram. [Citation Graph (, )][DBLP ] Efficient Implementation of Controlled Operations for Multivalued Quantum Logic. [Citation Graph (, )][DBLP ] Quantum Finite State Machines as Sequential Quantum Circuits. [Citation Graph (, )][DBLP ] Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates. [Citation Graph (, )][DBLP ] Mapping Binary Functions to a Practical Adiabatic Quantum Computer. [Citation Graph (, )][DBLP ] Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations. [Citation Graph (, )][DBLP ] Evolutionary approach to quantum symbolic logic synthesis. [Citation Graph (, )][DBLP ] Bi-Directional Synthesis of 4-Bit Reversible Circuits. [Citation Graph (, )][DBLP ] Search in 0.006secs, Finished in 0.010secs