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Publications of Author

1. Yibin Ye, Kaushik Roy, Rolf Drechsler
   Power Consumption in XOR-Based Circuits. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1999, pp:299-302 [Conf]
   
2. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
   Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:486-491 [Conf]
   
3. Yibin Ye, Kaushik Roy
   A Graph-Based Synthesis Algorithm for AND/XOR Networks. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:107-112 [Conf]
   
4. Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
   Dynamic noise analysis in precharge-evaluate circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:243- [Conf]
   
5. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
   Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:2-5 [Conf]
   
6. Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
   Mixed-V_th (MVT) CMOS Circuit Design Methodology for Low Power Applications. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:430-435 [Conf]
   
7. Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
   A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:253-257 [Conf]
   
8. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
   Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:592-595 [Conf]
   
9. Yibin Ye, Kaushik Roy, Georgios I. Stamoulis
   Quasi-static energy recovery logic and supply-clock generation circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1997, pp:96-99 [Conf]
   
10. Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
    Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
11. Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
    Design and optimization of dual-threshold circuits for low-voltage low-power applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:16-24 [Journal]
    
12. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, M. Stan, Vivek De
    Analysis of dual-V_T SRAM cells with full-swing single-ended bit line sensing for on-chip cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:91-95 [Journal]
    
13. 
    Incremental-Based Extreme Learning Machine Algorithms for Time-Variant Neural Networks. [Citation Graph (, )][DBLP]
    
    
14. 
    EasyFace: a realistic face modeling and facial animation authoring system. [Citation Graph (, )][DBLP]