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Publications of Author

1. Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
   Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:479-483 [Conf]
   
2. Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
   Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:166-171 [Conf]
   
3. Hiroaki Yoshida, Kaushik De, Vamsi Boppana
   Accurate pre-layout estimation of standard cell characteristics. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:208-211 [Conf]
   
4. H. Yoshida, H. Yamaoka, M. Ikeda, K. Asada
   Logic synthesis for PLA with 2-input logic elements. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2002, pp:373-376 [Conf]
   
5. Mayumi Oto, Masami Takata, Hiroaki Yoshida, Kazuki Joe
   A Quantum Algorithm for Searching Web Communities. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2002, pp:260-268 [Conf]
   
6. Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
   Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:479-483 [Conf]
   
7. Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
   Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:166-171 [Conf]
   
8. 
   Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. [Citation Graph (, )][DBLP]
   
   
9. 
   A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. [Citation Graph (, )][DBLP]
   
   
10. 
    Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. [Citation Graph (, )][DBLP]
    
    
11. 
    Some set partition statistics in non-crossing partitions and generating functions. [Citation Graph (, )][DBLP]