|
Search the dblp DataBase
Ko Yoshikawa:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura
Timing optimization by replacing flip-flops to latches. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:186-191 [Conf]
- Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:299-304 [Conf]
- Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa
Budgeting-free hierarchical design method for large scale and high-performance LSIs. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:955-958 [Conf]
- Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh
Timing Optimization on Mapped Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1991, pp:112-117 [Conf]
Search in 0.001secs, Finished in 0.001secs
|