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Cheong-fat Chan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-fat Chan, Kong-Pang Pun
    A low power asynchronous Java processor for contactless smart card. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:553-554 [Conf]
  2. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    A Totally Self-Checking Dynamic Asynchronous Datapath. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:27-32 [Conf]
  3. Pak-Kee Chan, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    Card-Centric Framework - Providing I/O Resources for Smart Cards. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:225-240 [Conf]
  4. Oliver Chiu-sing Choy, Tin-chak Pang, Juraj Povazanec, Cheong-fat Chan
    A Useful Micropipeline Architecture to Implement DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10212-0 [Conf]
  5. Wang Tung Cheng, Kong-Pang Pun, Cheong-fat Chan, Chiu-sing Choy
    An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1140-1143 [Conf]
  6. Wei Han, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    A speech recognizer with selectable model parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5842-5845 [Conf]
  7. Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Tan Lee, Chiu-sing Choy, Kong-Pang Pun, Pak-Chung Ching
    An HMM-based speech recognition IC. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:744-747 [Conf]
  8. Pak-Keung Leung, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:337-340 [Conf]
  9. Chi-Leung San, Chiu-sing Choy, Pak-Kee Chan, Cheong-fat Chan, Kong-Pang Pun
    Realization of card-centric framework: a card-centric computer [smart cards]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4999-5002 [Conf]
  10. Pui-Tak So, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    Ramp voltage supply using adiabatic charging principle. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2152-2155 [Conf]
  11. W. K. Yeung, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:185-187 [Conf]
  12. Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
    A low power asynchronous DES. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:538-541 [Conf]
  13. Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
    A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:910-913 [Conf]
  14. Lai-Kan Leung, Cheong-fat Chan, Oliver Chiu-sing Choy
    A giga-hertz CMOS digital controlled oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:610-613 [Conf]
  15. Wing-Kin Chan, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    An asynchronous SOVA decoder for wireless communication application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:517-520 [Conf]
  16. Kin-Pui Ho, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
    A CMOS current feedback operational amplifier with active current mode compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:709-712 [Conf]
  17. Hongwei Wang, Cheong-fat Chan, Chiu-sing Choy
    A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:137-140 [Conf]
  18. Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan, José E. Franca
    A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:221-224 [Conf]
  19. Wang-Chi Cheng, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A 1.2 V 900 MHz CMOS mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:365-368 [Conf]
  20. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Pipelines in Dynamic Dual-Rail Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:701-710 [Conf]
  21. Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-ling Yang, Tin-yan Tang
    Pipelined Dataflow Architecture of a Small Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1217-1223 [Conf]
  22. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Design for Self-Checking and Self-Timed Datapath. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:417-430 [Conf]
  23. Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-fat Chan
    A New Control Circuit for Asynchronous Micropipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:9, pp:992-997 [Journal]
  24. Jing-ling Yang, Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    A high-efficiency strongly self-checking asynchronous datapath. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1484-1494 [Journal]
  25. Pak-Keung Leung, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Wei Han, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    An efficient MFCC extraction method in speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Xiao-Yong He, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-fat Chan
    A 0.5V fully differential OTA with local common feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Siu-Kei Tang, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-fat Chan
    A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  29. Chi-Hong Chan, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Ke Xu, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  31. Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:3, pp:223-232 [Journal]

  32. Active RC filter with reduced capacitance by current division technique. [Citation Graph (, )][DBLP]


  33. 0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application. [Citation Graph (, )][DBLP]


  34. Adiabatic Smart Card. [Citation Graph (, )][DBLP]


  35. 0.8 V GPS band CMOS VCO with 29% Tuning Range. [Citation Graph (, )][DBLP]


  36. Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. [Citation Graph (, )][DBLP]


  37. A 900 MHz 1.2 V CMOS mixer with high linearity. [Citation Graph (, )][DBLP]


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